01
Respins cost weeks
A bug caught after fab means a board respin — roughly $50K and six weeks gone before you can even test the fix.
Hardware simulation
Simulate your entire hardware design with firmware in the loop.
HardLabs simulates your circuit with SPICE-grade behavioral models and runs your real firmware against it — so you catch integration and timing bugs days or weeks before a physical prototype is fabbed.
Built by engineers fromNVIDIABloombergAmazonStitch Fix
The problem
Bugs found late are the most expensive bugs you ship.
By the time firmware meets hardware on a real bench, the cheap window to fix things has closed. The bugs that live on the hardware/firmware boundary are exactly the ones nobody can see until both halves exist.
02
The boundary is invisible
Until the board and the firmware both exist, no one can see how they actually behave together — so integration risk hides until the worst possible moment.
03
Rigs don't exist yet
Bench and HIL setups are expensive, and you can't build one until the hardware is already in hand — so firmware waits on the board.
What we catch
The cross-domain bugs you can't see until bring-up.
On a complex board, the worst failures hide where firmware meets hardware — power, buses, pinmux, and timing. HardLabs runs your real firmware against the simulated circuit and fails the run when any of these break.
Power-sequence errors
Rails come up out of order.
I²C address conflicts
Two devices, one address.
Race conditions
An interrupt races a DMA transfer.
Pinmux errors
A pin wired to the wrong function.
HW / FW miscommunication
The driver and the board disagree.
Firmware regressions
A fix quietly breaks another path.
Bus timing violations
Clock-stretch, t_HIGH, and protocol limits exceeded.
Output contention
Two drivers fight the same line.
How it works
How firmware-in-the-loop testing works
01
Model your circuit
Import a netlist or build from datasheets. HardLabs generates behavioral models of your MCU, peripherals, and analog front end.
02
Run firmware in the loop
Flash your real firmware image into the simulated MCU. It executes against the circuit — GPIO, interrupts, I²C, SPI, and timers included.
03
Catch bugs before bring-up
Step through bus traffic, assert on timing, and scope any node. Fix integration bugs while they're still cheap to fix.
Map your netlist in minutes. Model what matters by hand.
Import from Cadence, Altium, KiCad, or a SPICE netlist — digital connectivity and bus topology come across almost instantly. Behavioral models for the analog parts that drive bring-up (PMICs, sensors, front ends) take longer; we tell you which is which, and you can request models we haven't built yet.
Imports
CadenceAltiumKiCadSPICE netlist
Firmware
.elf / .binsource + toolchainno code change
How it's different
SPICE shows you the circuit. Emulators run your firmware. Neither shows you the boundary.
The expensive bugs live where firmware meets analog — and today no single tool sees both halves at once.
vs. SPICE
SPICE simulates the circuit, but nothing is driving it the way your real firmware will. You verify the schematic, not the system.
vs. firmware emulators
Renode and QEMU run your firmware against idealized, register-level peripherals. The peripheral always behaves — so the timing and protocol violations that cause respins never show up.
vs. a HIL rig
A bench rig is the real thing, but it doesn't exist until the board does. By then the cheap window to fix integration bugs has already closed.
HardLabs runs your real firmware against an analog-aware circuit model and fails the build the moment a timing or protocol contract breaks — weeks before the first board is fabbed.
What it catches
Catches the bugs that cause respins.
The expensive bugs live on the timing and protocol boundary — a clock-stretch a peripheral won't tolerate, an interrupt that races a DMA transfer. HardLabs runs your firmware against the simulated circuit and fails the run the moment a contract breaks.
In an early design-partner project, an I²C clock-stretch violation surfaced four weeks before the first board was fabbed — exactly the miss that otherwise means a respin.
Model fidelity, stated plainly
Digital and bus connectivity map from your netlist almost immediately. Analog behavioral models — the parts that surface real timing and power-domain bugs — are hand-tuned to expose integration failures, not to replace final sign-off characterization. We tell you where each model's edges are.
Coverage at launch
Arm Cortex-M0 / M4 / M33I²CSPIUARTGPIO · timers · interruptsADC / PWMsensors · PMICs · bus devices
On the roadmap
Cortex-A · FPGAXpedition importPCIe · SerDes · DDREthernet PHY
What you get
Circuit simulation for firmware, with the depth to find real bugs.
Models
Behavioral peripheral models
SPICE-grade analog plus digital models for sensors, PMICs, and bus devices — accurate enough to surface real timing behavior.
Assertions
Firmware-in-the-loop assertions
Write checks that fail the build the moment firmware violates a timing or protocol contract — and produce traceable results you can tie back to requirements.
Bus
Decode & inspect bus traffic
Live I²C, SPI, and UART decode with a logic-analyzer view. No probes, no rig, no soldering.
Scope
Scope every node
Trace any signal over time, zoom to the edge, and measure exactly like a bench oscilloscope.
CI
Headless in CI
Run the full loop in CI so every firmware commit is regression-tested against the board.
Who it's for
Built for the people who own bring-up.
Embedded & firmware engineers
Write and test drivers the day the schematic freezes — not the day the board lands on your desk.
Hardware design engineers
Confirm firmware drives your circuit the way the datasheet promised, before you commit a design to fab.
EE managers
De-risk bring-up timelines by running hardware and firmware in parallel instead of in sequence.
Security
Built to run where your IP lives.
Your netlists and firmware stay yours — we don't train on customer designs. Self-hosted and on-prem deployment for export-controlled and IP-sensitive teams; talk to us about your environment.
Who's behind it
We've shipped the hardware, the firmware, and the ML that ties them together.
Agnieszka Szefer
Co-founder & CEO
Prev. Stitch Fix · Amazon · Bain Capital Ventures. Built ML systems in production at scale; runs how we turn datasheets into models.
Adam Szefer
Co-founder & CTO
Prev. Bloomberg · Gyfted. Systems and simulation infrastructure — the engine that runs your firmware against the circuit.
Design-partner program
A few design partners. One board, proven before fab.
We're onboarding a select group of hardware teams for our design-partner program. We build the simulation, run your firmware, and surface the respin-causing bugs before fab — you help shape the roadmap and keep the package we build. We'll agree on what success looks like for your board up front.
What we'll deliver
- A digital twin of your hardware, built from your netlist, schematic, and BOM.
- A virtual lab: scopes, logic analyzers, and firmware debuggers in simulation.
- Auto-flagging of power-sequence errors, output contention, and race conditions.
- Collaborative debugging with custom-built sim tools (early partners).
- Unlimited changes and revisions during the pilot.
What we need from you
- A netlist, schematic PDF, and BOM.
- One board or subsystem to scope the pilot.
- Your real firmware binaries — no model writing on your side.
Currently onboarding
Robotics & autonomyAerospace & defenseMedical devicesIndustrial & IoTConsumer hardwareData center & networking
Your netlists and firmware stay yours — we don't train on customer designs.
NDA-first. Export-control, on-prem, and air-gapped available on request.
Supports Cadence, Altium, KiCad, and all major MCU platforms.
Building hardware? Email us to join the pilot program.
aga@hardlabs.ioSend us one subsystem. We'll show you a bug we'd catch.
FAQ
Questions engineers ask first.
HardLabs combines SPICE-grade behavioral models for analog blocks with cycle-aware digital models for buses and MCUs. They're tuned to expose integration and timing bugs — not to replace final sign-off characterization.
At launch we cover common Arm Cortex-M families and the I²C, SPI, UART, GPIO, timer, and interrupt subsystems firmware leans on most. Peripheral and sensor model coverage expands every release.
SPICE simulates the circuit — it doesn't run your firmware. HardLabs executes your actual firmware image in the loop with the simulated circuit, so you test the hardware and the code together.
A HIL rig needs physical hardware and bench instruments that don't exist until late in the program. HardLabs is a hardware-in-the-loop alternative that runs entirely in software, before any board is fabbed.
No. The whole point is to start before a prototype exists. When real hardware arrives, the same firmware and test suite carry straight over to the bench.
Yes. The loop runs headless, so you can gate every firmware commit on the same circuit-level tests you'd otherwise only run by hand at bring-up.
Yes — talk to us. Self-hosted and on-prem deployment is available for export-controlled and IP-sensitive teams. Your netlists and firmware stay yours; we don't train on customer designs.
Cadence, Altium, and KiCad at launch — plus SPICE netlists and BOM/CSV imports. Allegro and Xpedition direct import is on the roadmap. Send us your netlist, schematic PDF, and BOM to get started.
Your netlist, schematic PDF, and BOM — plus your firmware (image or source). HardLabs builds the simulation and runs your code against it; you write no models.
Find the bug before the board exists.
Join the waitlist for early access to firmware-in-the-loop testing on simulated circuits.