HardLabs
Board simulator

Simulate whole PCBs with firmware-in-the-loop

Upload the schematic/netlist, BOM and firmware. HardLabs builds a simulator of your board and runs the real firmware against it.

atmos_g4 — board simulator
idle
Inputs
atmos.net
KiCad netlist
atmos.csv
BOM
payload.elf
firmware
Atmos G4 simulated topologyDPS368from BOMICM-42688from BOMBMP280from BOMW25N01GVfrom BOMSTM32G474Cortex-M4from netlistI²CSPISPISPI
$ Press Start
Watch HardLabs build the simulator.
Read designBuild board modelAttach modelsLoad firmwareRunDebug
Built by hardware and software engineers fromNVIDIABloombergAmazonStitch Fix

Hardware, firmware, simulation, and production developer infrastructure — the stack HardLabs needs.

Interactive system demo

Debug the whole system in software

Start the simulator, attach an ECG lead, connect USB, and inject motion. Watch the production firmware and simulated peripherals react together.

No hardware. No mocked firmware. This is the production ELF running against the simulated board.

live UARTLCDECGchargeraccelerometer
cardio_fw.elf · simulated board
running
UART0
HardLabs Cardio r5
ADS1292 ready · 250 SPS
MAX77654 battery 68%
ECG acquisition started
Monitor & log
# load cardio_fw.elf on simulated board
sysbus LoadELF cardio_fw.elf
simulation started · 6 live peripherals
# ECG lead attached → GPIO12
ECG LIVE68%
72 BPM
ECG lead
streaming · 250 SPS
Battery & charger
battery · 68%
Accelerometer
source off

What bugs does this find?

Catch an I²C timing violation in software

Replay the bus trace, inspect timing margins, and fail the firmware run when SCL violates the peripheral's contract.

Caught 4 weeks before fab on a design-partner board

hardlabs · bus timing
1 failed · 3 passed
Atmos G4 simulated topologyDPS368I²C · 0x76FAILICM-42688SPI1 · WHO_AM_IBMP280SPI3 · id 0x58W25N01GVSPI2 · JEDECSTM32G474Cortex-M4payload.elfI²CSPISPISPIPOWERBUSMCUFW
i2c1 · SCL / SDAfail
✓ spi1 ICM WHO_AM_I 0x47 ····· pass
✓ spi3 BMP280 id 0x58 ····· pass
✗ i2c1 SCL t_HIGH 0.42µs < 0.60µs FAIL
✓ spi2 W25N JEDEC ····· pass
at drivers/i2c.c:118 · fw pc 0x0800_1A4C

BUS · I²C clock stretchSCL t_HIGH 0.42µs < 0.60µs Fast-mode.

Headless in CI

From schematic to CI

Regression-test firmware against the simulated board on every commit.

hardlabs/atmos-firmware #142
i2c: tighten SCL high time
  • boot sequencequeued
  • spi1 WHO_AM_Iqueued
  • i2c1 SCL t_HIGHqueued
  • spi3 chip idqueued

Design-partner program

Send us your design. We'll send you a simulator.

Send schematic, netlist, BOM and firmware. We build a working board simulator you can run, debug and put in CI.

You send
  • schematic / netlist
  • BOM
  • firmware image
We send back
  • working board simulator
  • peripheral models
  • setup that runs your firmware
  • CI integration (pilot scope)

FAQ

Questions engineers ask first.

Schematic/netlist, BOM, and firmware (ELF/bin or source + toolchain). Cadence, Altium, and KiCad exports work at launch. You write no models.