JLC

Cimos·kicad-druid·JLCPCB/JLCPCB.kicad_pcb

JLC PCB layout, top view — open source board by Cimos

About the JLC PCB

JLC is an open source PCB design by Cimos, published on GitHub under the MIT license. It is a 4-layer board measuring 180 × 235 mm, with 1 components from 1 distinct parts.

From the project

KiCad custom design rules (.kicad_dru) matching JLCPCB and PCBWay manufacturing capabilities

KiCad custom design rules (.kicaddru) that match the manufacturing capabilities of common PCB fab houses. Rules are validated against a paired test board (.kicadpcb) so each rule has at least one footprint that passes or fails as expected.

The rules are authored against the KiCad 8 custom-rules syntax and are forward-compatible with KiCad 9 and 10 — every token used here is unchanged across those releases (KiCad 9/10 only add new constraints on top). If you're on KiCad 8, 9, or 10, they just work.

JLC bill of materials (BOM)

1 components, 1 distinct parts.

QtyPartRefs
1
1k
R1

JLC design files

The KiCad project lives in the Cimos/kicad-druid repository on GitHub; these links point at the commit this page was built from.

JLC: common questions

How big is the JLC PCB?

The JLC measures 180 × 235 mm, has 4 copper layers and is 1.6 mm thick.

How many components are on the JLC?

1 components, from 1 distinct parts. The full bill of materials is listed on this page.

Where can I download the JLC design files?

From the Cimos/kicad-druid repository on GitHub, which has the KiCad layout and the schematic; the links under Design files point to each one.

Can I use the JLC design in my own project?

Yes, under the terms of its MIT license, which Cimos chose for the repository.