Engineering

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Deep dives for people shipping firmware against real schematics — Renode platforms, HIL alternatives, and the bus timing bugs that cause respins. For narrative write-ups, see the blog.

• HIL alternative before hardware

  Need HIL-class coverage before PCBs exist? HardLabs runs unmodified firmware against a netlist-derived board model — a software HIL path for schematic freeze.

  Adam Szefer · 2026-07-20

• Renode board platforms

  Generate Renode board platforms from KiCad or Allegro netlists. Attach peripheral models, surface coverage gaps, and load a .repl without hand-maintaining every CS line.

  Adam Szefer · 2026-07-18

• Firmware-in-the-loop

  Firmware-in-the-loop against your netlist — not stubs. Run unmodified .elf images on MCU simulation with board-aware I²C/SPI models and CI assertions.

  Agnieszka Szefer · 2026-07-15

• Simulate firmware without hardware

  Simulate firmware without a board: where QEMU’s idealized peripherals fall short, and how board-level models catch pinmux and bus bugs before fab.

  Adam Szefer · 2026-07-22

• I²C clock stretching

  Diagnose I²C clock-stretch and t_HIGH violations before fab. Why STM32 masters and slow sensors disagree — and how simulation catches it early.

  Adam Szefer · 2026-07-21

• KiCad → simulation

  Take a KiCad netlist into firmware-in-the-loop simulation. Overlay the BOM, generate a Renode-oriented board platform, and test drivers before fab.

  Agnieszka Szefer · 2026-07-16

• Altium → simulation

  Simulate firmware against Altium-designed connectivity before fab. Use design-of-record exports — not a hand-maintained virtual shield.

  Agnieszka Szefer · 2026-07-16

• Simulate the PCB before fab

  Simulate your PCB before manufacturing: run real firmware against netlist-derived buses and catch pinmux, address, and timing bugs while the schematic can still change.

  Adam Szefer · 2026-07-14

• Avoid integration respins

  Avoid PCB respins caused by pinmux, bus, and timing mistakes — catch HW/FW integration bugs in simulation weeks before the first articles.

  Agnieszka Szefer · 2026-07-14

• Runnable PCB digital twin

  A PCB digital twin built from netlist and BOM — runnable under real firmware, with honest coverage gaps when a part is not modeled yet.

  Adam Szefer · 2026-07-15

• Embedded system simulation

  Embedded system simulation that includes your PCB buses and parts — not just the Cortex-M core — so drivers meet the real topology before hardware.

  Agnieszka Szefer · 2026-07-15

• Bring-up before the prototype

  Simulate board bring-up before the first prototype: power-on assumptions, bus enumeration, and firmware init against your netlist.

  Adam Szefer · 2026-07-17

• HW/SW co-simulation

  Hardware–software co-simulation that sees the boundary: real MCU firmware plus board-aware peripheral models from your netlist.

  Agnieszka Szefer · 2026-07-15

• I²C & SPI on your topology

  Simulate I²C and SPI with real firmware and netlist wiring — catch address conflicts, CS mistakes, and timing violations before the bench.

  Adam Szefer · 2026-07-17