How accurate are the simulations?

HardLabs combines SPICE-grade behavioral models for analog blocks with cycle-aware digital models for buses and MCUs. They're tuned to expose integration and timing bugs — not to replace final sign-off characterization.

Which MCUs and peripherals are supported?

At launch we cover common Arm Cortex-M families and the I²C, SPI, UART, GPIO, timer, and interrupt subsystems firmware leans on most. Peripheral and sensor model coverage expands every release.

How is this different from plain SPICE?

SPICE simulates the circuit — it doesn't run your firmware. HardLabs executes your actual firmware image in the loop with the simulated circuit, so you test the hardware and the code together.

How is this different from a hardware-in-the-loop (HIL) rig?

A HIL rig needs physical hardware and bench instruments that don't exist until late in the program. HardLabs is a hardware-in-the-loop alternative that runs entirely in software, before any board is fabbed.

Do I need any physical hardware?

No. The whole point is to start before a prototype exists. When real hardware arrives, the same firmware and test suite carry straight over to the bench.

Yes. The loop runs headless, so you can gate every firmware commit on the same circuit-level tests you'd otherwise only run by hand at bring-up.

Can we run this on-prem or air-gapped?

Yes — talk to us. Self-hosted and on-prem deployment is available for export-controlled and IP-sensitive teams. Your netlists and firmware stay yours; we don't train on customer designs.

Which EDA tools do you support?

Cadence, Altium, and KiCad at launch — plus SPICE netlists and BOM/CSV imports. Allegro and Xpedition direct import is on the roadmap. Send us your netlist, schematic PDF, and BOM to get started.

What do I provide to get started?

Your netlist, schematic PDF, and BOM — plus your firmware (image or source). HardLabs builds the simulation and runs your code against it; you write no models.

Will my RTOS and HALs run unchanged?

That is the goal for supported MCU families. Gaps are called out when a peripheral model or CPU platform is missing — we do not pretend coverage we do not have.

Firmware-in-the-loop on the board you actually drew

Agnieszka Szefer · Co-founder & CEOJuly 15, 2026Updated July 23, 2026

Prev. Stitch Fix · Amazon · Bain Capital Ventures. Built ML systems in production at scale; runs how we turn datasheets into models.

FITL only helps if both sides are honest. Stubbed HALs hide pinmux bugs. Always-ACK peripherals hide stretch and address mistakes. HardLabs runs the shipping image against models wired like your schematic.

SIL, FITL, and HIL — without the slideware

SIL usually replaces the MCU with a host process. HIL needs physical I/O. FITL here means MCU-accurate instruction execution plus peripherals that can fail the way silicon fails. If your “FITL” never NACKs, it is a unit test with extra steps.

What we take from your design package

Netlist for connectivity, BOM for MPNs, optional schematic docs for straps and addresses. Firmware as .elf/.bin. You do not rewrite drivers for the simulator.

Assertions that belong in CI

Protocol and timing contracts — stretch limits, forbidden register sequences, power-order assumptions encoded as checks — should fail the pipeline the same way a red bring-up does, only earlier.

FAQ

Will my RTOS and HALs run unchanged?: That is the goal for supported MCU families. Gaps are called out when a peripheral model or CPU platform is missing — we do not pretend coverage we do not have.

HardLabs

What HardLabs does — join the design-partner pilot

We build a digital twin from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break — weeks before bring-up on hardware.

A digital twin of your hardware, built from your netlist, schematic, and BOM.
A virtual lab: scopes, logic analyzers, and firmware debuggers in simulation.
Auto-flagging of power-sequence errors, output contention, and race conditions.

Pilot details · App

HIL alternative before hardware
Need HIL-class coverage before PCBs exist? HardLabs runs unmodified firmware against a netlist-derived board model — a software HIL path for schematic freeze.
Renode board platforms
Generate Renode board platforms from KiCad or Allegro netlists. Attach peripheral models, surface coverage gaps, and load a .repl without hand-maintaining every CS line.
Simulate firmware without hardware
Simulate firmware without a board: where QEMU’s idealized peripherals fall short, and how board-level models catch pinmux and bus bugs before fab.
HardLabs vs QEMU
The I²C Clock-Stretch Bug We Caught Four Weeks Before Fab

All topics

Firmware-in-the-loop on the board you actually drew

SIL, FITL, and HIL — without the slideware

What we take from your design package

Assertions that belong in CI

FAQ

What HardLabs does — join the design-partner pilot

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