HardLabs

Firmware-in-the-loop on the board you actually drew

Agnieszka Szefer · Co-founder & CEOUpdated July 23, 2026

Prev. Stitch Fix · Amazon · Bain Capital Ventures. Built ML systems in production at scale; runs how we turn datasheets into models.

FITL only helps if both sides are honest. Stubbed HALs hide pinmux bugs. Always-ACK peripherals hide stretch and address mistakes. HardLabs runs the shipping image against models wired like your schematic.

SIL, FITL, and HIL — without the slideware

SIL usually replaces the MCU with a host process. HIL needs physical I/O. FITL here means MCU-accurate instruction execution plus peripherals that can fail the way silicon fails. If your “FITL” never NACKs, it is a unit test with extra steps.

What we take from your design package

Netlist for connectivity, BOM for MPNs, optional schematic docs for straps and addresses. Firmware as .elf/.bin. You do not rewrite drivers for the simulator.

Assertions that belong in CI

Protocol and timing contracts — stretch limits, forbidden register sequences, power-order assumptions encoded as checks — should fail the pipeline the same way a red bring-up does, only earlier.

FAQ

Will my RTOS and HALs run unchanged?
That is the goal for supported MCU families. Gaps are called out when a peripheral model or CPU platform is missing — we do not pretend coverage we do not have.

HardLabs

Send us your design. We'll send you a simulator.

We build a board simulator from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break.

  • A working simulator of your board, built from netlist, schematic, and BOM.
  • Peripheral models attached so your firmware can talk to the board.
  • A setup that runs your real firmware binary — no rewrite required.

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