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THESIS-UltraLowPower-LoRa-Node

DimitraMTsakiridou·THESIS-UltraLowPower-LoRa-Node·Hardware/stm32wl5_karavakia/stm32wl5_karavakia.kicad_pcb

THESIS-UltraLowPower-LoRa-Node PCB layout, top view — open source STM32 board by DimitraMTsakiridou
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About the THESIS-UltraLowPower-LoRa-Node PCB

THESIS-UltraLowPower-LoRa-Node is an open source STM32 PCB design by DimitraMTsakiridou, published on GitHub. It is a 4-layer board measuring 90 × 50 mm, with 63 components from 37 distinct parts.

Its main chip is the STM32WL55JCI6, from the STM32 family. Other key parts include the TPS63802DLAT and BALFHB-WL-01D3. By type, the board carries 28 capacitors, 15 resistors, 8 connectors, 3 ICs, 3 diodes and 3 inductors.

It belongs with the rf & radio, iot & wireless and power & battery designs in this gallery.

From the project

Aiming to address the challenges of remote water quality monitoring and bypass the complexity of standard LoRaWAN networks, this repository contains the from-scratch design, end-to-end implementation, and extensive experimental evaluation of a custom, energy-autonomous LoRa telem

Aiming to address the challenges of remote water quality monitoring and bypass the complexity of standard LoRaWAN networks, this repository contains the from-scratch design, end-to-end implementation, and extensive experimental evaluation of a custom, energy-autonomous LoRa telemetry node.

THESIS-UltraLowPower-LoRa-Node, from the project README
From the project README

Main components on the THESIS-UltraLowPower-LoRa-Node

STM32WL55JCI6TPS63802DLATBALFHB-WL-01D3

THESIS-UltraLowPower-LoRa-Node bill of materials (BOM)

63 components, 37 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
STM32WL55JCI6
U1
1
TPS63802DLAT
U2
1
BALFHB-WL-01D3
U3
1
PMOS
Q1
1
32MHz
Y1
1
~
J1
5
~
J7, J8, J9, J10, J11
1
~
J12
1
SWD Header
J13
1
B3FS-1000P
S1
1
BLUE
D1
1
D_TVS
D2
1
GREEN
D3
1
47n
L1
1
470n
L3
1
15u
L4
1
100p
C1
11
100n
C3, C4, C5, C6, C9, C10, C15, C18 +3
1
10n
C8
3
4u7
C11, C16, C31
Show 17 more
QtyPartRefs
4
1u
C12, C29, C32, C33
2
12p
C13, C14
1
470n
C17
2
10u
C24, C30
1
22u
C25
1
68p
C27
1
47n
C28
2
4k7
R3, R4
1
220
R7
1
330
R8
2
100k
R9, R17
1
10k
R11
1
240
R12
4
22
R13, R16, R20, R21
1
47
R14
1
511k
R18
1
91k
R19

THESIS-UltraLowPower-LoRa-Node design files

The KiCad project lives in the DimitraMTsakiridou/THESIS-UltraLowPower-LoRa-Node repository on GitHub; these links point at the commit this page was built from.

THESIS-UltraLowPower-LoRa-Node: common questions

What microcontroller does the THESIS-UltraLowPower-LoRa-Node use?

The THESIS-UltraLowPower-LoRa-Node is built around the STM32WL55JCI6, from the STM32 family.

How big is the THESIS-UltraLowPower-LoRa-Node PCB?

The THESIS-UltraLowPower-LoRa-Node measures 90 × 50 mm, has 4 copper layers and is 1.196 mm thick.

How many components are on the THESIS-UltraLowPower-LoRa-Node?

63 components, from 37 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the THESIS-UltraLowPower-LoRa-Node design files?

From the DimitraMTsakiridou/THESIS-UltraLowPower-LoRa-Node repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the THESIS-UltraLowPower-LoRa-Node design in my own project?

The repository has no license, so all rights stay with DimitraMTsakiridou. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the THESIS-UltraLowPower-LoRa-Node without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug STM32 firmware against it before you order a PCB.

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