I²C clock stretching and timing violations
Prev. Bloomberg · Gyfted. Systems and simulation infrastructure — the engine that runs your firmware against the circuit.
Clock stretch is legal I²C — until your master timing assumptions meet a peripheral that holds SCL longer than your stack tolerates. Those bugs are miserable on the bench and inexpensive to catch when the bus exists only as a netlist.
What the failure looks like in the lab
Intermittent NACKs, transactions that work at 100 kHz and die at 400 kHz, or a scope that shows SCL low longer than your driver’s timeout. Teams often blame pull-ups first; sometimes the contract was wrong in software.
Why emulators miss it
If the peripheral model never stretches, your timeout path never runs. HardLabs models are built to exercise contracts that cause respins — including timing edges called out in the datasheet.
Encode the contract as a failing test
Once you have a trace, turn the limit into an assertion. The homepage teaser — t_HIGH 0.42µs against a 0.60µs floor — is the shape of the check. Ship it in CI so the next pinmux change cannot revive the bug.
FAIL i2c1 t_HIGH
measured 0.42 µs
required ≥ 0.60 µs (peripheral datasheet)
note stretch / master timing contract broken
caught 4 weeks before first fabFAQ
- Is every stretch a bug?
- No. Stretch is part of the protocol. The bug is a mismatch between what the slave does and what the master (or your timeouts) allow.
HardLabs
What HardLabs does — join the design-partner pilot
We build a digital twin from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break — weeks before bring-up on hardware.
- A digital twin of your hardware, built from your netlist, schematic, and BOM.
- A virtual lab: scopes, logic analyzers, and firmware debuggers in simulation.
- Auto-flagging of power-sequence errors, output contention, and race conditions.
Related
- Firmware-in-the-loop
Firmware-in-the-loop against your netlist — not stubs. Run unmodified .elf images on MCU simulation with board-aware I²C/SPI models and CI assertions.
- Simulate firmware without hardware
Simulate firmware without a board: where QEMU’s idealized peripherals fall short, and how board-level models catch pinmux and bus bugs before fab.
- HIL alternative before hardware
Need HIL-class coverage before PCBs exist? HardLabs runs unmodified firmware against a netlist-derived board model — a software HIL path for schematic freeze.
- The I²C Clock-Stretch Bug We Caught Four Weeks Before Fab
- INA219 model
