How accurate are the simulations?

HardLabs combines SPICE-grade behavioral models for analog blocks with cycle-aware digital models for buses and MCUs. They're tuned to expose integration and timing bugs — not to replace final sign-off characterization.

Which MCUs and peripherals are supported?

At launch we cover common Arm Cortex-M families and the I²C, SPI, UART, GPIO, timer, and interrupt subsystems firmware leans on most. Peripheral and sensor model coverage expands every release.

How is this different from plain SPICE?

SPICE simulates the circuit — it doesn't run your firmware. HardLabs executes your actual firmware image in the loop with the simulated circuit, so you test the hardware and the code together.

How is this different from a hardware-in-the-loop (HIL) rig?

A HIL rig needs physical hardware and bench instruments that don't exist until late in the program. HardLabs is a hardware-in-the-loop alternative that runs entirely in software, before any board is fabbed.

Do I need any physical hardware?

No. The whole point is to start before a prototype exists. When real hardware arrives, the same firmware and test suite carry straight over to the bench.

Yes. The loop runs headless, so you can gate every firmware commit on the same circuit-level tests you'd otherwise only run by hand at bring-up.

Can we run this on-prem or air-gapped?

Yes — talk to us. Self-hosted and on-prem deployment is available for export-controlled and IP-sensitive teams. Your netlists and firmware stay yours; we don't train on customer designs.

Which EDA tools do you support?

Cadence, Altium, and KiCad at launch — plus SPICE netlists and BOM/CSV imports. Allegro and Xpedition direct import is on the roadmap. Send us your netlist, schematic PDF, and BOM to get started.

What do I provide to get started?

Your netlist, schematic PDF, and BOM — plus your firmware (image or source). HardLabs builds the simulation and runs your code against it; you write no models.

I²C and SPI simulation on your real topology

Adam Szefer · Co-founder & CTOJuly 17, 2026Updated July 23, 2026

Prev. Bloomberg · Gyfted. Systems and simulation infrastructure — the engine that runs your firmware against the circuit.

Bus bugs are rarely in the MCU reference manual. They are in which chip sits on which bus with which address and CS. Simulation only helps when those facts come from the schematic.

What you can see before probes exist

Enumeration failures, NACKs, wrong addresses, CS polarity/GPIO mistakes, stretch and t_HIGH contracts — with decode instead of a logic analyzer on a half-built board.

Tied to the netlist, not a virtual shield

Attachments come from discovered buses in your design. A hand-maintained “shield” that drifts from the schematic trains drivers on fiction.

When timing is the bug

Clock stretch and master timeouts deserve their own deep dive — see the I²C timing topic and the design-partner post-mortem for a concrete t_HIGH failure.

SPI attach sketch (generated)

u4_bmp280: HIP.BMP280 @ spi3
    Cs => gpioPortA@15

HardLabs

What HardLabs does — join the design-partner pilot

We build a digital twin from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break — weeks before bring-up on hardware.

A digital twin of your hardware, built from your netlist, schematic, and BOM.
A virtual lab: scopes, logic analyzers, and firmware debuggers in simulation.
Auto-flagging of power-sequence errors, output contention, and race conditions.

Pilot details · App

I²C clock stretching
Diagnose I²C clock-stretch and t_HIGH violations before fab. Why STM32 masters and slow sensors disagree — and how simulation catches it early.
Renode board platforms
Generate Renode board platforms from KiCad or Allegro netlists. Attach peripheral models, surface coverage gaps, and load a .repl without hand-maintaining every CS line.
Firmware-in-the-loop
Firmware-in-the-loop against your netlist — not stubs. Run unmodified .elf images on MCU simulation with board-aware I²C/SPI models and CI assertions.
The I²C Clock-Stretch Bug We Caught Four Weeks Before Fab
BMP280 model

All topics

I²C and SPI simulation on your real topology

What you can see before probes exist

Tied to the netlist, not a virtual shield

When timing is the bug

What HardLabs does — join the design-partner pilot

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