Question 1

How accurate are the simulations?

Accepted Answer

HardLabs combines SPICE-grade behavioral models for analog blocks with cycle-aware digital models for buses and MCUs. They're tuned to expose integration and timing bugs — not to replace final sign-off characterization.

Question 2

Which MCUs and peripherals are supported?

Accepted Answer

At launch we cover common Arm Cortex-M families and the I²C, SPI, UART, GPIO, timer, and interrupt subsystems firmware leans on most. Peripheral and sensor model coverage expands every release.

Question 3

How is this different from plain SPICE?

Accepted Answer

SPICE simulates the circuit — it doesn't run your firmware. HardLabs executes your actual firmware image in the loop with the simulated circuit, so you test the hardware and the code together.

Question 4

How is this different from a hardware-in-the-loop (HIL) rig?

Accepted Answer

A HIL rig needs physical hardware and bench instruments that don't exist until late in the program. HardLabs is a hardware-in-the-loop alternative that runs entirely in software, before any board is fabbed.

Question 5

Do I need any physical hardware?

Accepted Answer

No. The whole point is to start before a prototype exists. When real hardware arrives, the same firmware and test suite carry straight over to the bench.

Question 6

Can I run it in CI?

Accepted Answer

Yes. The loop runs headless, so you can gate every firmware commit on the same circuit-level tests you'd otherwise only run by hand at bring-up.

Question 7

Can we run this on-prem or air-gapped?

Accepted Answer

Yes — talk to us. Self-hosted and on-prem deployment is available for export-controlled and IP-sensitive teams. Your netlists and firmware stay yours; we don't train on customer designs.

Question 8

Which EDA tools do you support?

Accepted Answer

Cadence, Altium, and KiCad at launch — plus SPICE netlists and BOM/CSV imports. Allegro and Xpedition direct import is on the roadmap. Send us your netlist, schematic PDF, and BOM to get started.

Question 9

What do I provide to get started?

Accepted Answer

Your netlist, schematic PDF, and BOM — plus your firmware (image or source). HardLabs builds the simulation and runs your code against it; you write no models.

Dimension	HardLabs	Renode alone
MCU / firmware execution	Uses Renode-class platforms for supported Cortex-M families	Excellent, mature CPU and platform library
Board description	Generated from netlist + BOM; gaps listed explicitly	Hand-written .repl / platform files
Peripheral fidelity	Datasheet-derived behavioral models with side effects	Varies — often simplified or missing for your exact MPN
CI assertions on timing/protocol	First-class (stretch, contracts, bring-up suites)	Possible, but you build the harness

HardLabs and Renode