ActiveLoad
try-except·TitoSync·ActiveLoad/ActiveLoadPCB/ActiveLoadPCB.kicad_pcb
About the ActiveLoad PCB
ActiveLoad is an open source PCB design by try-except, published on GitHub. It is a 2-layer board measuring 97 × 150.9 mm, with 57 components from 39 distinct parts.
Other key parts include the TPS551892QWRYQRQ1. By type, the board carries 29 resistors, 12 transistors, 7 capacitors, 5 connectors, 2 diodes and 1 IC.
Main components on the ActiveLoad
ActiveLoad bill of materials (BOM)
57 components, 39 distinct parts — part numbers from the project's BOM.
| Qty | Part | Footprint | Refs |
|---|---|---|---|
| 1 | TPS551892QWRYQRQ1 LM358 Texas Instruments | DIP-8_W7.62mm_Socket | U1 |
| 7 | 2N2222A | TO-92L_Inline_Wide | Q1, Q2, Q4, Q6, Q8, Q10, Q12 |
| 5 | TIP142 | TO-247-3_Vertical | Q3, Q5, Q7, Q9, Q11 |
| 1 | C7498454 Conn_01x03_Pin DORABO | PinHeader_1x03_P2.54mm_Vertical | J1 |
| 1 | CONN_01X02 Conn_01x03_Pin hanxia | PinHeader_1x03_P2.54mm_Vertical | J2 |
| 1 | CONN_01X03 Screw_Terminal_01x03 hanxia | TerminalBlock_MetzConnect_Type055_RT01503HDWU_1x03_P5.00mm_Horizontal | J3 |
| 1 | 12VOUT Screw_Terminal_01x02 DORABO | TerminalBlock_MetzConnect_Type055_RT01502HDWU_1x02_P5.00mm_Horizontal | J4 |
| 1 | Conn_01x03_Pin | PinHeader_1x03_P2.54mm_Vertical | J6 |
| 1 | 10k | Potentiometer | RV1 |
| 1 | LED | LED_D3.0mm | D2 |
| 1 | BZX85C3V3 | D_T-1_P5.08mm_Horizontal | D3 |
| 1 | 0.01UF 1n TDK | C_Disc_D5.0mm_W2.5mm_P2.50mm | C1 |
| 1 | 0.1UF 100u MuRata,TDK | CP_Radial_D5.0mm_P2.50mm | C2 |
| 2 | 0.1UF 10u MuRata,TDK | CP_Radial_D5.0mm_P2.50mm | C3, C6 |
| 1 | 0.1UF 100n Murata Electronics North America | C_Disc_D5.0mm_W2.5mm_P2.50mm | C4 |
| 1 | 4.7UF 100u MuRata | CP_Radial_D5.0mm_P2.50mm | C5 |
| 1 | 100PF 100n TDK | C_Disc_D5.0mm_W2.5mm_P2.50mm | C7 |
| 1 | 49.9 470 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R1 |
| 1 | 102K 470 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R2 |
| 1 | 11.3K 470 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R3 |
Show 19 more
| Qty | Part | Footprint | Refs |
|---|---|---|---|
| 1 | 49.9K 3.3k Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R4 |
| 1 | 150K 3.3k RESI | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R5 |
| 1 | 39k Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R6 |
| 1 | 15K 220 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R7 |
| 1 | 2.2k Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R8 |
| 1 | 10M 470 Bourns | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R9 |
| 1 | 147K 220 FOJAN | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R10 |
| 1 | 115K 33 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R11 |
| 1 | 102K 4.7 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R12 |
| 1 | 4.99K 0.5 Vishay-Dale | R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal | R13 |
| 1 | 4.99K 4.7 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R14 |
| 1 | 102K 0.5 Vishay-Dale | R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal | R15 |
| 3 | 220 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R16, R19, R25 |
| 2 | 49.9K 0.5 Vishay-Dale | R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal | R17, R21 |
| 1 | 12.7K 0.5 Vishay-Dale | R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal | R18 |
| 5 | 0.5 | R_Axial_DIN0309_L9.0mm_D3.2mm_P12.70mm_Horizontal | R20, R23, R24, R26, R27 |
| 1 | 2.7 220 Vishay-Dale | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R22 |
| 1 | 360 | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R28 |
| 1 | 100k | R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal | R29 |
ActiveLoad design files
The KiCad project lives in the try-except/TitoSync repository on GitHub; these links point at the commit this page was built from.
ActiveLoad: common questions
How big is the ActiveLoad PCB?
The ActiveLoad measures 97 × 150.9 mm, has 2 copper layers and is 1.6 mm thick.
How many components are on the ActiveLoad?
57 components, from 39 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.
Where can I download the ActiveLoad design files?
From the try-except/TitoSync repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.
Can I use the ActiveLoad design in my own project?
The repository has no license, so all rights stay with try-except. Use it as a reference, and ask the author before reusing the design.