Avoid PCB respins caused by HW/FW surprises
Prev. Stitch Fix · Amazon · Bain Capital Ventures. Built ML systems in production at scale; runs how we turn datasheets into models.
A respin is often an integration miss that could have been a failing test. Not every fab cycle is preventable — sensor yield and mechanical fit still bite — but pinmux typos and I²C contracts should not be why you wait six weeks.
Respin classes simulation can hit
Pinmux and connector mistakes, address collisions, CS/GPIO swaps, firmware init vs power order, protocol timing the peripheral rejects. Encode the ones that already burned you once as CI assertions.
What still needs a bench
Analog noise, RF, mechanical, and supplier variance. Use simulation to stop wasting first-article time on software/schematic disagreement so lab hours go to physics.
Make “won’t respin for that” measurable
When a partner catch lands — like an SCL t_HIGH floor violation — leave the check in the pipeline. The blog post-mortem is the narrative; the assertion is the insurance.
FAQ
- Can simulation eliminate respins?
- No. It eliminates a class of them: firmware and connectivity mismatches. Treat that as schedule insurance, not a guarantee.
HardLabs
Send us your design. We'll send you a simulator.
We build a board simulator from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break.
- A working simulator of your board, built from netlist, schematic, and BOM.
- Peripheral models attached so your firmware can talk to the board.
- A setup that runs your real firmware binary — no rewrite required.
Related
- Simulate the PCB before fab
Simulate your PCB before manufacturing: run real firmware against netlist-derived buses and catch pinmux, address, and timing bugs while the schematic can still change.
- I²C clock stretching
Diagnose I²C clock-stretch and t_HIGH violations before fab. Why STM32 masters and slow sensors disagree — and how simulation catches it early.
- Firmware-in-the-loop
Firmware-in-the-loop against your netlist — not stubs. Run unmodified .elf images on MCU simulation with board-aware I²C/SPI models and CI assertions.
- The I²C Timing Bug We Caught Four Weeks Before Fab
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