How accurate are the simulations?

HardLabs combines SPICE-grade behavioral models for analog blocks with cycle-aware digital models for buses and MCUs. They're tuned to expose integration and timing bugs — not to replace final sign-off characterization.

Which MCUs and peripherals are supported?

At launch we cover common Arm Cortex-M families and the I²C, SPI, UART, GPIO, timer, and interrupt subsystems firmware leans on most. Peripheral and sensor model coverage expands every release.

How is this different from plain SPICE?

SPICE simulates the circuit — it doesn't run your firmware. HardLabs executes your actual firmware image in the loop with the simulated circuit, so you test the hardware and the code together.

How is this different from a hardware-in-the-loop (HIL) rig?

A HIL rig needs physical hardware and bench instruments that don't exist until late in the program. HardLabs is a hardware-in-the-loop alternative that runs entirely in software, before any board is fabbed.

Do I need any physical hardware?

No. The whole point is to start before a prototype exists. When real hardware arrives, the same firmware and test suite carry straight over to the bench.

Yes. The loop runs headless, so you can gate every firmware commit on the same circuit-level tests you'd otherwise only run by hand at bring-up.

Can we run this on-prem or air-gapped?

Yes — talk to us. Self-hosted and on-prem deployment is available for export-controlled and IP-sensitive teams. Your netlists and firmware stay yours; we don't train on customer designs.

Which EDA tools do you support?

Cadence, Altium, and KiCad at launch — plus SPICE netlists and BOM/CSV imports. Allegro and Xpedition direct import is on the roadmap. Send us your netlist, schematic PDF, and BOM to get started.

What do I provide to get started?

Your netlist, schematic PDF, and BOM — plus your firmware (image or source). HardLabs builds the simulation and runs your code against it; you write no models.

PCB simulation before fab

Adam Szefer · Co-founder & CTOJuly 14, 2026Updated July 23, 2026

Prev. Bloomberg · Gyfted. Systems and simulation infrastructure — the engine that runs your firmware against the circuit.

Most teams SPICE fragments of the design or emulate an MCU in isolation. Neither is “simulate the PCB.” Board-level simulation means the topology in your netlist — CS lines, shared buses, part identity — under the firmware you intend to ship.

What has to be true for pre-fab simulation to matter

Connectivity from the design of record, MPNs from the BOM, and peripherals that can NACK or stretch when silicon would. A pretty 3D board view is not simulation. Neither is a DRC clean sheet.

Failures worth finding before copper

Wrong alternate functions, two devices on one address, SPI CS on the wrong GPIO, init order that races a rail, bus timing the part will not tolerate. Those are respin-class. RF and sensor physics still need articles.

A workflow at schematic freeze

Export netlist + BOM, generate a platform, load firmware, run the bring-up checks you already planned for the lab. Keep the suite in CI so the next ECO cannot reintroduce a fixed bug.

Generate → load (sketch)

# after HardLabs generate
(monitor) include @compiled/BMP280.cs
(monitor) mach create
(monitor) machine LoadPlatformDescription @board.repl
(monitor) sysbus LoadELF @bringup.elf

HardLabs

What HardLabs does — join the design-partner pilot

We build a digital twin from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break — weeks before bring-up on hardware.

A digital twin of your hardware, built from your netlist, schematic, and BOM.
A virtual lab: scopes, logic analyzers, and firmware debuggers in simulation.
Auto-flagging of power-sequence errors, output contention, and race conditions.

Pilot details · App

Simulate firmware without hardware
Simulate firmware without a board: where QEMU’s idealized peripherals fall short, and how board-level models catch pinmux and bus bugs before fab.
Avoid integration respins
Avoid PCB respins caused by pinmux, bus, and timing mistakes — catch HW/FW integration bugs in simulation weeks before the first articles.
Bring-up before the prototype
Simulate board bring-up before the first prototype: power-on assumptions, bus enumeration, and firmware init against your netlist.
The I²C Clock-Stretch Bug We Caught Four Weeks Before Fab

All topics

PCB simulation before fab

What has to be true for pre-fab simulation to matter

Failures worth finding before copper

A workflow at schematic freeze

What HardLabs does — join the design-partner pilot

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