PCB simulation before fab

Adam Szefer · Co-founder & CTOUpdated July 23, 2026

Prev. Bloomberg · Gyfted. Systems and simulation infrastructure — the engine that runs your firmware against the circuit.

Most teams SPICE fragments of the design or emulate an MCU in isolation. Neither is “simulate the PCB.” Board-level simulation means the topology in your netlist — CS lines, shared buses, part identity — under the firmware you intend to ship.

What has to be true for pre-fab simulation to matter

Connectivity from the design of record, MPNs from the BOM, and peripherals that can NACK or stretch when silicon would. A pretty 3D board view is not simulation. Neither is a DRC clean sheet.

Failures worth finding before copper

Wrong alternate functions, two devices on one address, SPI CS on the wrong GPIO, init order that races a rail, bus timing the part will not tolerate. Those are respin-class. RF and sensor physics still need articles.

A workflow at schematic freeze

Export netlist + BOM, build the simulated board, load firmware, run the bring-up checks you already planned for the lab. Keep the suite in CI so the next ECO cannot reintroduce a fixed bug.

Build → run (sketch)
# after the board is built: the bring-up checks, one fresh boot each
npx hardlabs run checks/bringup.scenario.yaml --firmware build/bringup.elf

HardLabs

Send us your design. We'll send you a simulator.

We build a board simulator from your netlist, schematic, and BOM, run your real firmware against it, and fail CI when pinmux, buses, or timing contracts break.

  • A working simulator of your board, built from netlist, schematic, and BOM.
  • Peripheral models attached so your firmware can talk to the board.
  • A setup that runs your real firmware binary — no rewrite required.

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