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LARS-Hardware-Interface

CAuDri·LARS-Hardware-Interface·PCB/KiCad/hardware_interface.kicad_pcb

LARS-Hardware-Interface PCB layout, top view — open source STM32 board by CAuDri
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About the LARS-Hardware-Interface PCB

LARS-Hardware-Interface is an open source STM32 PCB design by CAuDri, published on GitHub under the GPL-3.0 license. It is a 6-layer board measuring 86 × 86 mm, with 247 components from 61 distinct parts.

Its main chip is the STM32F429ZIT6TR, from the STM32 family. Other key parts include the TPS2117DRLR, MIC2039AYM6, OPA2834IDGKR, SN74S1051DR and USBLC6-2SC6. By type, the board carries 94 resistors, 70 capacitors, 31 connectors, 28 diodes, 12 ICs and 2 jumpers.

From the project

This repository contains the schematic, PCB design files and a basic firmware stack for the Hardware Interface of the Lightweight Autonomous Racing System (LARS).

This repository contains the schematic, PCB design files and a basic firmware stack for the Hardware Interface of the Lightweight Autonomous Racing System (LARS).

The board is based on a STM32F4 microcontroller and is designed to interface with various sensors and actuators on the vehicle. The communication with the host PC is done via USB, using micro-ROS and the underlying micro-XRCE DDS.

LARS-Hardware-Interface, from the project README
From the project README

Main components on the LARS-Hardware-Interface

STM32F429ZIT6TRTPS2117DRLRMIC2039AYM6OPA2834IDGKRSN74S1051DRUSBLC6-2SC6TCAN1057AVDRQ1

LARS-Hardware-Interface bill of materials (BOM)

247 components, 61 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
STM32F429ZIT6TR
U1
1
TPS2117DRLR
U2
1
MIC2039AYM6
MIC2039AYM6-TR
U3
2
OPA2834IDGKR
U4, U5
4
SN74S1051DR
U6, U7, U8, U9
2
USBLC6-2SC6
U10, U12
1
TCAN1057AVDRQ1
U11
1
IQXO-791 8.00MHz
Y1
1
Reset Header
J1
1
SWD Flash
J2
1
XT30
J3
2
CAN1
J4, J5
2
SPI1
J6, J7
4
I2C1
J8, J9, J10, J11
1
TIM1
J12
1
TIM2
J13
4
I2C2
J14, J15, J16, J17
1
3.3V Out
J18
1
5V Out
J19
1
UART1
J20
Show 41 more
QtyPartRefs
1
UART2
J21
1
UART3
J22
1
Servo 1
J23
1
Servo 2
J24
1
GPIO
J25
1
Analog 1
J26
1
Analog 2
J27
1
USB1
J28
1
USB2
J29
1
LED1
J30
1
LED2
J31
1
LD1117AS33TR
CR1
4
BAT54SFILM
CR2, CR3, CR4, CR5
1
2920L400
F1
1
CAN1
JP1
1
USB Power
JP2
1
Reset
SW1
1
User Button
SW2
9
TVS
D1, D5, D7, D8, D9, D10, D11, D14 +1
3
Red
D2, D17, D23
3
5V6
D3, D4, D6
3
0.7V
D12, D25, D26
1
3V3
D13
6
Green
D15, D16, D18, D20, D21, D22
1
Blue
D19
2
WS2812B
D27, D28
1
FBMH2012HM221-T8
FB1
52
100N
100n
C1, C3, C4, C8, C9, C10, C11, C12 +44
7
2U2
2u2
C2, C5, C6, C24, C26, C67, C68
7
10U
10u
C7, C21, C23, C25, C27, C54, C55
1
100U
100u
C22
1
10N
10n
C28
2
NA
C29, C33
4
10K
10k
R1, R4, R7, R86
20
1k
R2, R6, R9, R13, R14, R16, R18, R19 +12
46
220
R3, R15, R20, R25, R26, R27, R28, R29 +38
1
0R
R5
7
5K1
5k1
R8, R10, R11, R79, R80, R84, R85
8
120
R12, R23, R24, R45, R46, R70, R71, R77
2
NA
R17, R22
6
2K2
2k2
R47, R48, R72, R73, R76, R83

LARS-Hardware-Interface design files

The KiCad project lives in the CAuDri/LARS-Hardware-Interface repository on GitHub; these links point at the commit this page was built from.

LARS-Hardware-Interface: common questions

What microcontroller does the LARS-Hardware-Interface use?

The LARS-Hardware-Interface is built around the STM32F429ZIT6TR, from the STM32 family.

How big is the LARS-Hardware-Interface PCB?

The LARS-Hardware-Interface measures 86 × 86 mm, has 6 copper layers and is 1.71 mm thick.

How many components are on the LARS-Hardware-Interface?

247 components, from 61 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the LARS-Hardware-Interface design files?

From the CAuDri/LARS-Hardware-Interface repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the LARS-Hardware-Interface design in my own project?

Yes, under the terms of its GPL-3.0 license, which CAuDri chose for the repository.

Can I test firmware for the LARS-Hardware-Interface without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug STM32 firmware against it before you order a PCB.

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