HardLabs

Clock test

joshajohnson·ecp5-mini·breakouts/clock-test-0.1/clock-test.kicad_pcb

Clock test PCB layout, top view — open source FPGA board by joshajohnson

About the Clock test PCB

Clock test is an open source FPGA PCB design by joshajohnson, published on GitHub under the CERN-OHL-S-2.0 license. It is a 2-layer board measuring 99.8 × 99.8 mm, with 83 components from 7 distinct parts.

Its main chip is the S7 Mini, from the FPGA family. By type, the board carries 60 diodes, 16 resistors, 3 transistors, 3 connectors and 1 switch.

From the project

ECP5 FPGA in an "S7 Mini" form factor

ECP5 Mini is a Lattice ECP5 FPGA in the Black Mesa Labs "S7 Mini" form factor.

r0.1 is depreciated. ~~hardware has been assembled with no major issues being found at time of writing. Requires more validation, particularly the HyperRAM, microSD, and signal integrity of IO.~~

r0.2 moves to 1v8 HyperRAM along with major IO changes to improve performance. Pinout is not compatiable with r0.1, but mechanically is identical. Projects utiliting the features of the board to be completed.

Clock test, from the project README
From the project README

Clock test bill of materials (BOM)

83 components, 7 distinct parts.

QtyPartRefs
3
DMG2302U
Q1, Q2, Q3
1
PWR
J1
2
S7 Mini
J3, J4
1
SW_Push
SW1
60
FM-B2020RGBA-HG
2020RGBA
Foshan NationStar Optoelectronics
D1, D2, D3, D4, D5, D6, D7, D8 +52
15
470R
RN1, RN2, RN3, RN4, RN5, RN6, RN7, RN8 +7
1
10K
RN16

Clock test design files

The KiCad project lives in the joshajohnson/ecp5-mini repository on GitHub; these links point at the commit this page was built from.

Clock test: common questions

What microcontroller does the Clock test use?

The Clock test is built around the S7 Mini, from the FPGA family.

How big is the Clock test PCB?

The Clock test measures 99.8 × 99.8 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the Clock test?

83 components, from 7 distinct parts. The full bill of materials is listed on this page.

Where can I download the Clock test design files?

From the joshajohnson/ecp5-mini repository on GitHub, which has the KiCad layout and the schematic; the links under Design files point to each one.

Can I use the Clock test design in my own project?

Yes, under the terms of its CERN-OHL-S-2.0 license, which joshajohnson chose for the repository.

Can I test firmware for the Clock test without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.

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