HardLabs

RailLink Adapter

Misaka0x2730·RailLink·hardware-adapter/source/RailLink_Adapter.kicad_pcb

RailLink Adapter PCB layout, top view — open source board by Misaka0x2730
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About the RailLink Adapter PCB

RailLink Adapter is an open source PCB design by Misaka0x2730, published on GitHub under the CERN-OHL-P-2.0 license. It is a 2-layer board measuring 42 × 35 mm, with 7 components from 7 distinct parts.

It belongs with the usb & debug tools designs in this gallery.

From the project

Compact isolated version of J-Link v9.

RailLink Adapter, from the project README
From the project README

RailLink Adapter bill of materials (BOM)

7 components, 7 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
RailLink
J1
1
10-pin Cortex Debug
J2
1
TC2030-IDC-NL
J3
1
Standard JTAG
J4
1
20-pin Cortex Debug + ETM
J5
1
UART
J6
1
Ilya
J7

RailLink Adapter design files

The KiCad project lives in the Misaka0x2730/RailLink repository on GitHub; these links point at the commit this page was built from.

RailLink Adapter: common questions

How big is the RailLink Adapter PCB?

The RailLink Adapter measures 42 × 35 mm, has 2 copper layers and is 1.176 mm thick.

How many components are on the RailLink Adapter?

7 components, from 7 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the RailLink Adapter design files?

From the Misaka0x2730/RailLink repository on GitHub, which has the KiCad layout and the BOM; the links under Design files point to each one.

Can I use the RailLink Adapter design in my own project?

Yes, under the terms of its CERN-OHL-P-2.0 license, which Misaka0x2730 chose for the repository.

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