HardLabs

SteiStat

mabooo18·SteiStat·Hardware/STEI_Bstat_v1.2.kicad_pcb

SteiStat PCB layout, top view — open source RP2040/RP2350 board by mabooo18

About the SteiStat PCB

SteiStat is an open source RP2040/RP2350 PCB design by mabooo18, published on GitHub. It is a 2-layer board measuring 45 × 60 mm, with 31 components from 20 distinct parts.

Its main chip is the XIAO-RP2040-DIP, from the RP2040/RP2350 family. Other key parts include the AD5941BCPZ-RL7. By type, the board carries 19 capacitors, 4 resistors, 2 ICs, 2 inductors and 1 test point.

From the project

This folder contains the full KiCad hardware design source for the Steistat potentiostat carrier board (STEIBstatv1.2), consolidated from a previous separate export folder.

This folder contains the full KiCad hardware design source for the Steistat potentiostat carrier board (STEIBstatv1.2), consolidated from a previous separate export folder.

- STEIBstatv1.2.kicadsch / .kicadpcb / .kicadpro / .kicadprl / .kicaddru / .net — the KiCad project itself (schematic, PCB layout, project settings, design rules, netlist). Open STEIBstatv1.2.kicadpro in KiCad to edit. - Production/bom-1.csv and Production/positions.csv — the current, machine-generated Bill of Materials and pick-and-place file, exported directly from the PCB above. This is the BOM used in the project's…

Main components on the SteiStat

AD5941BCPZ-RL7XIAO-RP2040-DIP

SteiStat bill of materials (BOM)

31 components, 20 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
AD5941BCPZ-RL7
AD5941BCPZ
Analog Devices
U1
1
XIAO-RP2040-DIP
U2
1
200
RCAL1
1
4.7K
RCAL2
1
10K
RCAL3
1
TestPoint
TP1
2
FerriteBead
FB1, FB2
1
220PF
100n
Samsung
C1
2
470NF
100n
Samsung
C2, C3
8
100NF
100n
Samsung
C4, C5, C6, C8, C9, C10, C12, C17
1
470NF
470n
Samsung
C7
1
470NF
10u
Samsung
C11
2
100NF
470n
Samsung
C13, C15
1
4.7UF
470n
Samsung
C14
1
10UF
4,7u
Samsung
C16
1
100NF
220p
Samsung
C18
1
100NF
33n
Samsung
C19
2
1206W0R0
10K
UniOhm
R1, R2
1
1206W0R0
560
UniOhm
R3
1
10K
R4

SteiStat design files

The KiCad project lives in the mabooo18/SteiStat repository on GitHub; these links point at the commit this page was built from.

SteiStat: common questions

What microcontroller does the SteiStat use?

The SteiStat is built around the XIAO-RP2040-DIP, from the RP2040/RP2350 family.

How big is the SteiStat PCB?

The SteiStat measures 45 × 60 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the SteiStat?

31 components, from 20 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the SteiStat design files?

From the mabooo18/SteiStat repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the SteiStat design in my own project?

The repository has no license, so all rights stay with mabooo18. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the SteiStat without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug RP2040/RP2350 firmware against it before you order a PCB.

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