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Testing ESP32C6 in a XIAO footprint

martinberlin·H-C6-ulp·C6-40-Flash-test/C6-40-Flash-test.kicad_pcb

Testing ESP32C6 in a XIAO footprint PCB layout, top view — open source ESP32 board by martinberlin

About the Testing ESP32C6 in a XIAO footprint PCB

Testing ESP32C6 in a XIAO footprint is an open source ESP32 PCB design by martinberlin, published on GitHub under the GPL-3.0 license. It is a 4-layer board measuring 19.7 × 31.1 mm, with 23 components from 19 distinct parts.

Its main chip is the C5153500, from the ESP32 family. Other key parts include the MX25R1635FZUIL0_TR and C12044. By type, the board carries 7 capacitors, 7 resistors, 3 ICs, 2 connectors, 2 inductors and 1 crystal.

It belongs with the displays & leds designs in this gallery.

From the project

ESP32C6 in a very low power design with a 24 pin FPC for a small SPI Epaper

This PCB design is based on C6 design guidelines and uses the Buck converter schematic of Seeed XIAO C6 SGM6029

Failed release v1.0: We forgot to add SPI flash. Oh yeah, you won't flash it!

Testing ESP32C6 in a XIAO footprint, from the project README
From the project README

Main components on the Testing ESP32C6 in a XIAO footprint

MX25R1635FZUIL0_TRC5153500C12044

Testing ESP32C6 in a XIAO footprint bill of materials (BOM)

23 components, 19 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
MX25R1635FZUIL0_TR
IC1
1
C5153500
ESP32-C6
U2
1
C12044
MCP1700-3302E_SOT23
U3
1
C555614
Crystal 40 Mhz 10ppm
X1
1
C165948
USB_C_Receptacle_USB2.0
J1
1
SM04B-SRSS-TB(LF)(SN)
SM04B-SRSS-TB_LF__SN_
J4
1
C325005
SW_Push_Dual
SW1
1
C5252358
L
L1
1
C329586
L
L2
1
C162161
22pF
C1
2
C6119874
22pF
C2, C3
2
C5119318
10uF
C4, C5
2
C1779
0.1uF
C6, C7
1
C23186
5.1k
R1
2
C25804
10k
R2, R7
1
C6945215
10k
R3
1
C25804
0Ω
R4
1
5.1k
R5
1
C21189
10k
R6

Testing ESP32C6 in a XIAO footprint design files

The KiCad project lives in the martinberlin/H-C6-ulp repository on GitHub; these links point at the commit this page was built from.

Testing ESP32C6 in a XIAO footprint: common questions

What microcontroller does the Testing ESP32C6 in a XIAO footprint use?

The Testing ESP32C6 in a XIAO footprint is built around the C5153500, from the ESP32 family.

How big is the Testing ESP32C6 in a XIAO footprint PCB?

The Testing ESP32C6 in a XIAO footprint measures 19.7 × 31.1 mm, has 4 copper layers and is 1.6 mm thick.

How many components are on the Testing ESP32C6 in a XIAO footprint?

23 components, from 19 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the Testing ESP32C6 in a XIAO footprint design files?

From the martinberlin/H-C6-ulp repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the Testing ESP32C6 in a XIAO footprint design in my own project?

Yes, under the terms of its GPL-3.0 license, which martinberlin chose for the repository.

Can I test firmware for the Testing ESP32C6 in a XIAO footprint without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug ESP32 firmware against it before you order a PCB.

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