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VoxLink - Lattice Core Module

MichalVarsanyi·VoxLink·Hardware/Core_Module/Core_Module.kicad_pcb

VoxLink - Lattice Core Module layout, top view — open source FPGA board by MichalVarsanyi
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About the VoxLink - Lattice Core Module

VoxLink - Lattice Core Module is an open source FPGA PCB design by MichalVarsanyi, published on GitHub under the MIT license. It is a 6-layer board measuring 13 × 13 mm, with 52 components from 15 distinct parts.

Its main chip is the ICE40UL1K-CM36AI, from the FPGA family. Other key parts include the TPS7A20L_1V2, TPS7A20L_2V5, TPS7A20L_3V3 and W25Q32JV. By type, the board carries 28 diodes, 13 capacitors, 5 ICs, 5 resistors and 1 crystal.

It belongs with the sensors designs in this gallery.

From the project

VoxLink is a high-speed solution that allows interfacing of up to 100 sensors using a single high-speed host device. The communication protocol is agnostic to the sensor board, freeing the user from handling low-level communication. This project is part of my Bachelor's thesis at the Czech Technical University in Prague.

- During programming, exceeding internal clocking speeds of 100MHz on the iCE40UL1K-CM36AI FPGA proved to be virtually impossible. In the future, instantiating the hard IP I2C blocks in the FPGA silicon may increase the speed. Realistically, however, switching to a higher speed grade of FPGAs will probably be the best option.

It may seem that 50-100 MHz is unreasonably fast; however, just 40 sensors at 9 kHz get very close to this ballpark. It is difficult to determine what may increase the bandwidth in the future, so it's better to have an excess than to have too little bandwidth.…

VoxLink - Lattice Core Module, from the project README
From the project README

Main components on the VoxLink - Lattice Core Module

TPS7A20L_1V2ICE40UL1K-CM36AITPS7A20L_2V5TPS7A20L_3V3W25Q32JV

VoxLink - Lattice Core Module bill of materials (BOM)

52 components, 15 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
TPS7A20L_1V2
TI
U101
1
ICE40UL1K-CM36AI
Lattice
U102
1
TPS7A20L_2V5
TI
U103
1
TPS7A20L_3V3
TI
U104
1
W25Q32JV
Winbond
U105
1
12MHZ
12MHz
Abracon
Y101
2
LED
Kingbright
D101, D102
25
C2939949
TVS
Infineon
D201, D202, D203, D204, D205, D206, D207, D209 +17
1
C2939949
TSV
Infineon
D208
6
100N
100n
Murata
C101, C103, C107, C112, C113, C116
6
1u
Murata
C104, C105, C108, C109, C114, C115
1
2.2U
2.2u
Murata
C110
1
22R
Vishay
R101
2
499R
Vishay
R103, R106
2
10K
10k
Vishay
R104, R105

VoxLink - Lattice Core Module design files

The KiCad project lives in the MichalVarsanyi/VoxLink repository on GitHub; these links point at the commit this page was built from.

VoxLink - Lattice Core Module: common questions

What microcontroller does the VoxLink - Lattice Core Module use?

The VoxLink - Lattice Core Module is built around the ICE40UL1K-CM36AI, from the FPGA family.

How big is the VoxLink - Lattice Core Module?

The VoxLink - Lattice Core Module measures 13 × 13 mm, has 6 copper layers and is 1.2 mm thick.

How many components are on the VoxLink - Lattice Core Module?

52 components, from 15 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the VoxLink - Lattice Core Module design files?

From the MichalVarsanyi/VoxLink repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the VoxLink - Lattice Core Module design in my own project?

Yes, under the terms of its MIT license, which MichalVarsanyi chose for the repository.

Can I test firmware for the VoxLink - Lattice Core Module without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.

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