Gate to glass
OoEthanoO·gate-to-glass·hw/kicad/gtg_reva.kicad_sch
About the Gate to glass PCB
Gate to glass is an open source FPGA PCB design by OoEthanoO, published on GitHub. It is a board, with 49 components from 19 distinct parts.
Its main chip is the ICE40UP5K-SG48ITR, from the FPGA family. Other key parts include the 3.3V, 1.2V, 32MBIT and 12MHZ. By type, the board carries 18 capacitors, 10 resistors, 9 switches, 5 ICs, 4 connectors and 3 diodes.
From the project
gtgreva.kicadsch is generated from hw/netlist.csv by tools/gensch.py`. Do not edit it as a source file — regenerate it.
gtgreva.kicadsch is generated from hw/netlist.csv by tools/gensch.py`. Do not edit it as a source file — regenerate it.
tools/checkhw.py` validates the netlist against the FPGA package, the BOM and the RTL's port list. It cannot check what KiCad checks: that a power input is actually driven, that pin types are compatible, that a symbol's units are all placed. Two checkers with different blind spots beat one careful one.
Main components on the Gate to glass
Gate to glass bill of materials (BOM)
49 components, 19 distinct parts — part numbers from the project's BOM.
| Qty | Part | Footprint | Refs |
|---|---|---|---|
| 1 | ICE40UP5K-SG48ITR | QFN-48-1EP_7x7mm_P0.5mm_EP5.3x5.3mm_ThermalVias | U1 |
| 1 | 3.3V | SOT-23-5 | U2 |
| 1 | 1.2V | SOT-23-5 | U3 |
| 1 | 32MBIT 32Mbit | SOIC-8_3.9x4.9mm_P1.27mm | U4 |
| 1 | 12MHZ 12MHz | Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm_HandSoldering | U5 |
| 1 | USB_C_Receptacle_USB2.0_16P | USB_C_Receptacle_HRO_TYPE-C-31-M-12 | J1 |
| 1 | 2X5 2x5 | PinHeader_2x05_P2.54mm_Vertical | J2 |
| 1 | 1X8 1x8 | PinSocket_1x08_P2.54mm_Vertical | J3 |
| 1 | AudioJack3 | Jack_3.5mm_PJ320D_Horizontal | J4 |
| 9 | SW_Push | SW_PUSH_6mm | SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8 +1 |
| 1 | red | LED_0603_1608Metric | D1 |
| 2 | green | LED_0603_1608Metric | D2, D3 |
| 4 | 10UF 10uF | C_0805_2012Metric | C1, C2, C4, C17 |
| 12 | 100NF 100nF | C_0603_1608Metric | C3, C5, C6, C7, C8, C9, C10, C11 +4 |
| 2 | 10NF 10nF | C_0603_1608Metric | C15, C16 |
| 2 | 5.1K 5.1k | R_0603_1608Metric | R1, R2 |
| 2 | 10K 10k | R_0603_1608Metric | R3, R4 |
| 5 | 1k | R_0603_1608Metric | R5, R6, R7, R8, R9 |
| 1 | 100R | R_0603_1608Metric | R10 |
Gate to glass design files
The KiCad project lives in the OoEthanoO/gate-to-glass repository on GitHub; these links point at the commit this page was built from.
- Schematichw/kicad/gtg_reva.kicad_sch
- Netlisthw/kicad/gtg_reva.net
- BOMhw/bom.csv
Gate to glass: common questions
What microcontroller does the Gate to glass use?
The Gate to glass is built around the ICE40UP5K-SG48ITR, from the FPGA family.
How many components are on the Gate to glass?
49 components, from 19 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.
Where can I download the Gate to glass design files?
From the OoEthanoO/gate-to-glass repository on GitHub, which has the schematic, a netlist and the BOM; the links under Design files point to each one.
Can I use the Gate to glass design in my own project?
The repository has no license, so all rights stay with OoEthanoO. Use it as a reference, and ask the author before reusing the design.
Can I test firmware for the Gate to glass without the hardware?
Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.
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