HardLabs

Pergola

pergola-fpga·pergola·hardware/RevA/RevA.kicad_pcb

Pergola PCB layout, top view — open source FPGA board by pergola-fpga
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About the Pergola PCB

Pergola is an open source FPGA PCB design by pergola-fpga, published on GitHub under the MIT license. It is a 4-layer board measuring 85 × 54 mm, with 136 components from 39 distinct parts.

Its main chip is the LFE5U-12F-6BG256C, from the FPGA family. Other key parts include the SY8120B1ABC, XC6206P25, SPI Flash W25Q128JVSIQ, MIMXRT1011DAE5A and MAX803SQ308T1G. By type, the board carries 47 resistors, 44 capacitors, 10 ICs, 9 jumpers, 9 diodes and 5 connectors.

It belongs with the dev boards & breakouts designs in this gallery.

From the project

Low-cost ECP5 FPGA development board

The Pergola FPGA board is a low-cost, open-source FPGA development board featuring the Lattice ECP5 FPGA.

A handful of units have been built for initial test and bringup populated with LFE5U-12F-8BG256C.

It has been tested and works if the fixes below are applied.

- iMX ROM bootloader freezes because the UART RX pin is pulled low by the FPGA during boot. (FPGA pin is PL35BVREF16) A 4K7 pull-up is probably not enough, the voltage drops to 2.9V. Workaround: Bodge a 1K pull-up between UARTRX and 3V3. - Wrong load caps for the xtal. Should be 20pF. - SWD IO and CLK are swapped on the silk. -…

Pergola, from the project README
From the project README

Main components on the Pergola

SY8120B1ABCXC6206P25SPI Flash W25Q128JVSIQMIMXRT1011DAE5AMAX803SQ308T1GSPI RAM LY68L6400SLITLFE5U-12F-6BG256C16MHz 20ppm

Pergola bill of materials (BOM)

136 components, 39 distinct parts — part numbers from the project's BOM.

QtyPartRefs
2
SY8120B1ABC
U1, U3
1
XC6206P25
U2
1
SPI Flash W25Q128JVSIQ
U4
1
MIMXRT1011DAE5A
U5
1
MAX803SQ308T1G
U6
2
SPI RAM LY68L6400SLIT
U7, U10
1
LFE5U-12F-6BG256C
U8
1
16MHz 20ppm
U9
1
24MHz 10ppm
Y1
1
USB_C_RECEPTACLE_USB2.0
USB_C_Receptacle_USB2.0
J1
1
DNP Conn_02x02_Odd_Even
J2
2
DNP Conn_01x02
J3, J5
1
DNP Conn_02x03_Odd_Even
J4
9
4K7
JP1, JP2, JP3, JP4, JP5, JP6, JP7, JP8 +1
5
CONN_02X06_TOP_BOTTOM
Conn_02x06_Top_Bottom
PMOD1, PMOD2, PMOD3, PMOD4, PMOD5
2
SW_Push
SW1, SW2
1
LED_ARGB
D1
8
LED
D2, D3, D4, D5, D6, D7, D8, D9
1
Ferrite_Bead
FB1
3
4u7 1A
L1, L2, L3
Show 19 more
QtyPartRefs
21
100N
100n
C1, C3, C16, C17, C20, C23, C30, C31 +13
7
220N
220n
C2, C5, C8, C9, C13, C18, C19
3
4U7
4u7
C4, C10, C15
8
22U
22u
C6, C7, C12, C25, C26, C27, C28, C29
2
4P7
20p
C11, C14
2
22P
22p
C21, C22
1
10U
10u
C24
1
100K
R1
7
10K
R2, R3, R13, R14, R15, R16, R17
3
1K
R4, R36, R37
7
4K7
R5, R18, R19, R23, R24, R33, R34
2
5K1
R6, R7
1
30K
R8
2
15K
R9, R11
1
18K
R10
1
3K3
R12
11
4K7
10K
R20, R21, R22, R25, R26, R27, R28, R29 +3
1
DNP
R35
10
22R_X4
22R_x4
RN1, RN2, RN3, RN4, RN5, RN6, RN7, RN8 +2

Pergola design files

The KiCad project lives in the pergola-fpga/pergola repository on GitHub; these links point at the commit this page was built from.

Pergola: common questions

What microcontroller does the Pergola use?

The Pergola is built around the LFE5U-12F-6BG256C, from the FPGA family.

How big is the Pergola PCB?

The Pergola measures 85 × 54 mm, has 4 copper layers and is 1.2 mm thick.

How many components are on the Pergola?

136 components, from 39 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the Pergola design files?

From the pergola-fpga/pergola repository on GitHub, which has the KiCad layout and the BOM; the links under Design files point to each one.

Can I use the Pergola design in my own project?

Yes, under the terms of its MIT license, which pergola-fpga chose for the repository.

Can I test firmware for the Pergola without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.

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