Core64 LB v0.6

ageppert·Core-64-Interactive-Core-Memory-Badge·Electronic Design/Core64 LB v0.6/Core64 LB v0.6.kicad_pcb

Core64 LB v0.6 PCB layout, top view — open source NXP board by ageppert

About the Core64 LB v0.6 PCB

Core64 LB v0.6 is an open source NXP PCB design by ageppert, published on GitHub under the GPL-3.0 license. It is a 2-layer board measuring 85 × 170 mm, with 136 components from 52 distinct parts.

Its main chip is the Teensy3.2, from the NXP family. Other key parts include the LM393, SN74HC02DR, SN74LV1T125DBVR, M24C02-RMN and LP3961EMP-5.0. By type, the board carries 56 resistors, 22 transistors, 14 connectors, 12 diodes, 12 capacitors and 9 crystals.

It belongs with the wearables designs in this gallery, and the repository also holds 3 earlier revisions of it.

From the project

64 bits of core memory and LEDs to interact with directly using a magnetic wand.

Native KiCad files for the schematic and PCB. (KiCad Version: (5.1.2-1)-1, release build)

Main components on the Core64 LB v0.6

Core64 LB v0.6 bill of materials (BOM)

136 components, 52 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
LM393
U1
1
SN74HC02DR
U2
1
SN74LV1T125DBVR
U3
1
M24C02-RMN
U4
1
LP3961EMP-5.0
U5
1
TPS7A0533PDBVR
U6
1
Teensy3.2
U7
1
74HC238
U8
10
MMBT4403LT1G
Q1, Q3, Q5, Q7, Q9, Q11, Q13, Q15 +2
10
MMBT4401LT1G
Q2, Q4, Q6, Q8, Q10, Q12, Q14, Q16 +2
1
NVTR4503NT1G_NMOS_GSD
Q21
1
MCC_SL3401A_PMOS_GSD
Q22
1
Micro_LiPo_Charger
X1
1
HEADER_11-PIN_0.1
X2
1
Adafruit_3.2_TFT_1743
X3
2
HEADER_8-PIN_0.1
X4, X5
1
Header_9-PIN_0.1
X6
1
SSW-104-22-L-S-VS
X7
1
QWIIC
X8
1
SAO_conn_SFH11-NBPC-D03-ST-BK
X9
Show 32 more
QtyPartRefs
2
SSW-116-22-F-S-VS‎
J1, J2
4
Conn_01x01_Male
J3, J4, J10, J11
1
CORE Cur. Mon.
J5
1
SENSE DEBUG
J6
1
S03B-PASK-2_LF__SN_
J7
1
5V0 Cur. Mon.
J8
1
3V3 Cur. Mon.
J9
1
Power Rails
J12
1
PRG
J13
1
TEENSY Cur. Mon.
J14
1
3V
BT1
1
JS102011SAQN
SW1
1
PDZ10BGWX_(10V)
Z1
6
BAT54AW
D1, D3, D5, D7, D9, D11
6
BAT54CW
D2, D4, D6, D8, D10, D12
2
470UF
470uF
C1, C9
1
0.1UF
0.1uF
C2
1
10UF
10uF
C3
4
0.1uF
C4, C5, C6, C12
1
0.01uF
C7
1
68UF
68uF
C8
2
1UF
1uF
C10, C11
20
470
R1, R2, R3, R4, R5, R6, R7, R8 +12
6
6R8-5%
R21, R22, R23, R24, R25, R26
2
470
R27, R38
6
10K
R28, R39, R44, R45, R46, R47
3
1K5-1%
R29, R34, R35
2
1K8-1%
R30, R31
2
11-1%
R32, R33
4
1K2
R36, R37, R55, R56
9
10K
R40, R41, R42, R43, R50, R51, R52, R53 +1
2
68
R48, R49

Core64 LB v0.6 design files

The KiCad project lives in the ageppert/Core-64-Interactive-Core-Memory-Badge repository on GitHub; these links point at the commit this page was built from.

Core64 LB v0.6: common questions

What microcontroller does the Core64 LB v0.6 use?

The Core64 LB v0.6 is built around the Teensy3.2, from the NXP family.

How big is the Core64 LB v0.6 PCB?

The Core64 LB v0.6 measures 85 × 170 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the Core64 LB v0.6?

136 components, from 52 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the Core64 LB v0.6 design files?

From the ageppert/Core-64-Interactive-Core-Memory-Badge repository on GitHub, which has the KiCad layout and the BOM; the links under Design files point to each one.

Can I use the Core64 LB v0.6 design in my own project?

Yes, under the terms of its GPL-3.0 license, which ageppert chose for the repository.

Can I test firmware for the Core64 LB v0.6 without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug NXP firmware against it before you order a PCB.

More boards in Core-64-Interactive-Core-Memory-Badge

Earlier revisions in the repo: Core64 LB v0.5, Core64 LB v0.4, Core64 LB

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