ReDIP-CIA
daglem·reDIP-CIA·hardware/reDIP-CIA.kicad_pcb
About the ReDIP-CIA PCB
ReDIP-CIA is an open source FPGA PCB design by daglem, published on GitHub under the CERN-OHL-S-2.0 license. It is a 4-layer board measuring 17.8 × 50.8 mm, with 43 components from 16 distinct parts.
Its main chip is the ICE5LP1K-SG48ITR, from the FPGA family. Other key parts include the NCP115AMX120TCG, NCP115AMX330TCG, SN74CBT16210CDGGR, 74AHCT1G14SE-7 and AT25EU0011A-SSHN-T. By type, the board carries 21 resistors, 12 capacitors, 7 ICs, 2 connectors and 1 diode.
It belongs with the retro computing designs in this gallery.
From the project
MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA replacement
Lattice iCE5LP1K FPGA 1Mbit FLASH * 5V tolerant I/O
The reDIP CIA provides an open source hardware platform for MOS 6520 PIA / MOS 6522 VIA / MOS 6526/8520/8521 CIA replacements.
Designs for the iCE5LP1K FPGA can be processed by yosys and nextpnr.
5V input 35 FPGA GPIO 3 FPGA open-drain I/O GND
All FPGA header I/O is 5V tolerant, and can drive 5V TTL.
A separate header footprint is provided for (Q)SPI flash programming, with pinout borrowed from the iCEBreaker Bitsy.

Main components on the ReDIP-CIA
ReDIP-CIA bill of materials (BOM)
43 components, 16 distinct parts — part numbers from the project's BOM.
| Qty | Part | Footprint | Refs |
|---|---|---|---|
| 1 | NCP115AMX120TCG | CASE_711AJ_1.0x1.0mm_P0.65mm | U1 |
| 1 | NCP115AMX330TCG | CASE_711AJ_1.0x1.0mm_P0.65mm | U2 |
| 2 | SN74CBT16210CDGGR | TSSOP-48_6.1x12.5mm_P0.5mm | U3, U4 |
| 1 | 74AHCT1G14SE-7 74AHCT1G14 | SOT-353_SC-70-5 | U5 |
| 1 | ICE5LP1K-SG48ITR ICE5LP1K-SG48 | QFN-48-1EP_7x7mm_P0.5mm_EP5.6x5.6mm | U6 |
| 1 | AT25EU0011A-SSHN-T AT25EU0011A-SSHN | SOIC-8_3.9x4.9mm_P1.27mm | U7 |
| 2 | X5511WV-20-C35D35-1000 Conn_01x20 | PinHeader_1x20_P2.54mm_Vertical_Machined | J1, J2 |
| 1 | BAS16W-7-F BAS16W | SOT-323_SC-70 | D1 |
| 2 | GRM155C81C225KE11D 1uF | C_0402_1005Metric | C1, C3 |
| 2 | GRM033C80J105ME05D 1uF | C_0201_0603Metric | C2, C11 |
| 1 | GRM035R61A225ME01D 1uF | C_0201_0603Metric | C4 |
| 7 | GRM033R60J224ME90D 0.1uF | C_0201_0603Metric | C5, C6, C7, C8, C9, C10, C12 |
| 16 | ERJ1GNJ472C 4.7k | R_0201_0603Metric | R1, R2, R3, R4, R5, R6, R7, R8 +8 |
| 2 | ERJ1GNF2871C 2.87k | R_0201_0603Metric | R17, R21 |
| 1 | ERJ1GNJ101C 100 | R_0201_0603Metric | R18 |
| 2 | ERJ1GNJ103C 10k | R_0201_0603Metric | R19, R20 |
ReDIP-CIA design files
The KiCad project lives in the daglem/reDIP-CIA repository on GitHub; these links point at the commit this page was built from.
ReDIP-CIA: common questions
What microcontroller does the ReDIP-CIA use?
The ReDIP-CIA is built around the ICE5LP1K-SG48ITR, from the FPGA family.
How big is the ReDIP-CIA PCB?
The ReDIP-CIA measures 17.8 × 50.8 mm, has 4 copper layers and is 1.6062 mm thick.
How many components are on the ReDIP-CIA?
43 components, from 16 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.
Where can I download the ReDIP-CIA design files?
From the daglem/reDIP-CIA repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.
Can I use the ReDIP-CIA design in my own project?
Yes, under the terms of its CERN-OHL-S-2.0 license, which daglem chose for the repository.
Can I test firmware for the ReDIP-CIA without the hardware?
Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.
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