HardLabs

FD

Jegeva·FuzzyDuck·hardware/FD/FD.kicad_pcb

FD PCB layout, top view — open source FPGA board by Jegeva

About the FD PCB

FD is an open source FPGA PCB design by Jegeva, published on GitHub. It is a 6-layer board measuring 100 × 139 mm, with 270 components from 66 distinct parts.

Its main chip is the XC7A100T-FGG484, from the FPGA family. Other key parts include the AT93C66C, FT2232HQ, NCP59744-DFN10, 74LX1G00 and SWITCH_DP3T. By type, the board carries 103 resistors, 100 capacitors, 26 connectors, 17 ICs, 11 diodes and 6 transistors.

From the project

If it quacks like a duck, and is fuzzy to the touch...

Main components on the FD

AT93C66CFT2232HQNCP59744-DFN1074LX1G00SWITCH_DP3TAP2303XC7A100T-FGG484NLSX3018MT25Q128-8-ESF_SO16MT41K512M8DA-107P

FD bill of materials (BOM)

270 components, 66 distinct parts.

QtyPartRefs
1
AT93C66C
U1
1
FT2232HQ
U2
5
NCP59744-DFN10
U3, U6, U7, U8, U9
1
74LX1G00
U4
1
SWITCH_DP3T
U5
1
AP2303
U10
1
XC7A100T-FGG484
U11
4
NLSX3018
U12, U13, U14, U15
1
MT25Q128-8-ESF_SO16
U16
1
MT41K512M8DA-107P
U17
6
DMG2301L
Q2, Q3, Q4, Q5, Q6, Q7
1
ASTMLPE-18-100.000MHZ-LJ-E-T
X1
1
ASTMLPE-18-133.333MHZ-LJ-E-T
X2
1
12 MHz
Y1
1
USB_B_Micro
J1
1
ATX-24
J2
4
Conn_01x05
J3, J4, J5, J6
4
Conn_01x02_Male
J7, J8, J9, J10
5
Conn_01x01_Male
J11, J12, J13, J19, J20
5
Conn_01x05
J14, J15, J16, J21, J22
Show 46 more
QtyPartRefs
2
M.2_Socket_M
J25, J29
1
Conn_01x05_Male
J30
1
Conn_02x16_Counter_Clockwise
J31
1
Conn_01x06_Male
J32
1
Conn_02x03_Counter_Clockwise
J33
1
SW_SPDT
SW1
1
SW_SPST
SW2
3
LED_Small
D1, D2, D9
2
LED
D3, D4
6
MMSZ4678-TPMSCT-ND‎
D5, D6, D7, D8, D10, D11
2
600R/100MHz
L1, L2
2
4.7uF TA
C1, C4
13
100nF
C2, C5, C66, C68, C70, C71, C72, C73 +5
7
10nF
C3, C6, C65, C67, C69, C76, C77
2
20pF
C7, C8
12
4.7uF
C9, C10, C11, C12, C13, C14, C15, C16 +4
2
15pF
C20, C24
8
100uF
C22, C27, C40, C42, C43, C44, C48, C50
14
0.47uF
C23, C25, C26, C28, C30, C31, C32, C35 +6
3
0.1uF
C36, C38, C39
5
5.6nF
C41, C45, C46, C47, C51
7
10uF
C49, C52, C74, C78, C84, C85, C86
25
200nF
C53, C54, C55, C56, C57, C59, C60, C61 +17
7
10k
R1, R2, R3, R10, R31, R38, R40
1
2.2k
R4
1
12k
R5
6
1k
R6, R52, R53, R57, R58, R59
4
220
R7, R8, R12, R17
5
4.7k
R9, R44, R47, R50, R51
15
47k
R18, R19, R20, R21, R22, R23, R24, R25 +7
1
2.5k
R28
2
5k
R30, R39
2
12.5k
R32, R41
1
4.53k
R36
1
1.13k
R37
1
3.3k
R45
1
49.9
R46
7
100
R48, R49, R54, R55, R56, R60, R61
1
200
R62
2
1.8k
R63, R64
4
50
R65, R66, R67, R68
1
240
R69
16
R_Small
R73, R74, R75, R76, R77, R78, R79, R80 +8
1
68
R88
16
1k x4
RN1, RN2, RN3, RN4, RN5, RN6, RN7, RN8 +8
7
1k x4
RN17, RN18, RN19, RN20, RN21, RN22, RN23

FD design files

The KiCad project lives in the Jegeva/FuzzyDuck repository on GitHub; these links point at the commit this page was built from.

FD: common questions

What microcontroller does the FD use?

The FD is built around the XC7A100T-FGG484, from the FPGA family.

How big is the FD PCB?

The FD measures 100 × 139 mm, has 6 copper layers and is 1.2 mm thick.

How many components are on the FD?

270 components, from 66 distinct parts. The full bill of materials is listed on this page.

Where can I download the FD design files?

From the Jegeva/FuzzyDuck repository on GitHub, which has the KiCad layout and the schematic; the links under Design files point to each one.

Can I use the FD design in my own project?

The repository has no license, so all rights stay with Jegeva. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the FD without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.

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