HardLabs

Icepool board

jkiv·icepool-board·hardware/icepool-board.kicad_pcb

Icepool board layout, top view — open source FPGA board by jkiv
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About the Icepool board

Icepool board is an open source FPGA PCB design by jkiv, published on GitHub under the CC-BY-NC-4.0 license. It is a 4-layer board measuring 140 × 58 mm, with 116 components from 37 distinct parts.

Its main chip is the iCE40HX8K-BG121(121-Ball_caBGA), from the FPGA family. Other key parts include the FT2232HL-REEL, AP7361C_SOT-89-5, TPS62132 and 93LCxxC. By type, the board carries 43 capacitors, 36 resistors, 22 connectors, 6 ICs, 3 diodes and 2 crystals.

It belongs with the dev boards & breakouts designs in this gallery.

From the project

KiCad designs for the icepool project.

KiCad 5 design files for the icepool project.

icepool is a FPGA cluster and development board.

- 16x headers for daughter boards. - An FT2232H for USB communication and parallel FPGA flashing. - One-to-many SPI interface for sending data from the PC to each daughter board. - Daisy-chained SPI interface for passing data to and from the PC and each daughter board. - A 6-pin ATX +12V power connector for use with conventional PC power supplies.

Icepool board, from the project README
From the project README

Main components on the Icepool board

FT2232HL-REELAP7361C_SOT-89-5TPS6213293LCxxCiCE40HX8K-BG121(121-Ball_caBGA)

Icepool board bill of materials (BOM)

116 components, 37 distinct parts.

QtyPartRefs
1
FT2232HL-REEL
U1
2
AP7361C_SOT-89-5
U2, U7
1
TPS62132
U3
1
93LCxxC
U4
1
iCE40HX8K-BG121(121-Ball_caBGA)
U8
2
ASEM1-12.000MHZ
X1, X2
1
USB_B_Micro
J1
1
USE_VBUS_5V
J2
1
PCIe_6pin
J3
16
Conn_02x08_Odd_Even
J4, J5, J6, J7, J8, J9, J10, J11 +8
1
Conn_02x08_Odd_Even
J20
1
PWR_ALT
J21
1
~READY
J22
2
FSW
JP2, JP3
1
USE_VBUS_LED
D1
1
LED_IND
D2
1
PWRLED
D3
1
FB
FB1
1
2.2u
L1
8
4.7u
C1, C3, C7, C11, C12, C21, C22, C43
Show 17 more
QtyPartRefs
25
0.1u
C2, C4, C5, C6, C8, C13, C14, C16 +17
1
0.01u
C9
2
DNP
C10, C17
1
47u
C15
2
10u
C31, C35
1
10u
C37
1
3.3u
C38
1
0.1u
C39
1
22u
C41
7
4k7
R1, R6, R25, R32, R33, R34, R36
8
22R
R2, R3, R4, R5, R7, R8, R11, R13
1
12k
R9
7
DNP
R10, R24, R26, R27, R28, R29, R30
4
100k
R12, R21, R22, R23
2
1k
R14, R35
2
100R
R15, R16
5
10k
R17, R18, R19, R20, R31

Icepool board design files

The KiCad project lives in the jkiv/icepool-board repository on GitHub; these links point at the commit this page was built from.

Icepool board: common questions

What microcontroller does the Icepool board use?

The Icepool board is built around the iCE40HX8K-BG121(121-Ball_caBGA), from the FPGA family.

How big is the Icepool board?

The Icepool board measures 140 × 58 mm, has 4 copper layers and is 1.6 mm thick.

How many components are on the Icepool board?

116 components, from 37 distinct parts. The full bill of materials is listed on this page.

Where can I download the Icepool board design files?

From the jkiv/icepool-board repository on GitHub, which has the KiCad layout; the links under Design files point to each one.

Can I use the Icepool board design in my own project?

It is published under CC-BY-NC-4.0, which limits how it may be reused; read the license before building on it.

Can I test firmware for the Icepool board without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.

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