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Eis capstone

stevfu·eis_capstone·Helpstat/HELPStat_V2.kicad_pcb

Eis capstone PCB layout, top view — open source ESP32 board by stevfu

About the Eis capstone PCB

Eis capstone is an open source ESP32 PCB design by stevfu, published on GitHub under the MIT license. It is a 2-layer board measuring 102 × 45 mm, with 39 components from 20 distinct parts.

Its main chip is the ESP32-S3-DEVKITC-1-N8R2, from the ESP32 family. Other key parts include the MCP73831T-2ACI/OT, AP2112K-3.3TRG1 and AD5941BCPZ-RL7. By type, the board carries 16 capacitors, 8 connectors, 4 ICs, 4 resistors, 2 LEDs and 1 diode.

From the project

Utilization of Electrochemical Impedance Spectroscopy for the Detection of Drugs

Main components on the Eis capstone

MCP73831T-2ACI/OTAP2112K-3.3TRG1AD5941BCPZ-RL7ESP32-S3-DEVKITC-1-N8R2

Eis capstone bill of materials (BOM)

39 components, 20 distinct parts.

QtyPartRefs
1
MCP73831T-2ACI/OT
U2
1
AP2112K-3.3TRG1
U3
1
AD5941BCPZ-RL7
U4
1
ESP32-S3-DEVKITC-1-N8R2
U5
1
10118192-0001LF
J1
1
B2B-XH-A:JST_B2B-XH-A
LIPO1
J2
3
M20-9990246
J3, J4, J5
3
61300411121
J6, J7, J8
3
61300411121
I2C0, SPI0, UART0
1
BSS205NH6327XTSA1
MOSFET1
1
GY PSLM31.13-HQHS-5F5G-L2M2-100-R18
YLW
LED1
1
GT PSLM31.13-HRHT-26-KM-100-R18
GRN
LED2
1
BAT20JFILM
D1
5
LMK107BBJ106MALT
10u
C3, C4, C5, C6, C17
1
CL10B105KP8NNNC
1u
C7
4
TMK107B7474KA-TR
470n
C8, C9, C10, C12
1
LMK107BJ475KA-T
4.7u
C11
5
CC0603KRX7R7BB104
100n
C18, C19, C20, C21, C22
1
RC0603FR-07100KL
100k
R4
3
RC0603FR-074K7L
4k7
R7, R8, R9

Eis capstone design files

The KiCad project lives in the stevfu/eis_capstone repository on GitHub; these links point at the commit this page was built from.

Eis capstone: common questions

What microcontroller does the Eis capstone use?

The Eis capstone is built around the ESP32-S3-DEVKITC-1-N8R2, from the ESP32 family.

How big is the Eis capstone PCB?

The Eis capstone measures 102 × 45 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the Eis capstone?

39 components, from 20 distinct parts. The full bill of materials is listed on this page.

Where can I download the Eis capstone design files?

From the stevfu/eis_capstone repository on GitHub, which has the KiCad layout and the schematic; the links under Design files point to each one.

Can I use the Eis capstone design in my own project?

Yes, under the terms of its MIT license, which stevfu chose for the repository.

Can I test firmware for the Eis capstone without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug ESP32 firmware against it before you order a PCB.

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