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SupaClock Carrier v1 - PCB 67x85mm

ArticunoFruna·SupaClock_IEE2463·hardware/SupaClock_Carrier_v4/SupaClock_MainBoard/SupaClock_MainBoard.kicad_pcb

SupaClock Carrier v1 - PCB 67x85mm layout, top view — open source ESP32 board by ArticunoFruna
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About the SupaClock Carrier v1 - PCB 67x85mm

SupaClock Carrier v1 - PCB 67x85mm is an open source ESP32 PCB design by ArticunoFruna, published on GitHub. It is a 2-layer board measuring 40 × 48 mm, with 30 components from 21 distinct parts.

Its main chip is the XIAO-ESP32-S3, from the ESP32 family. Other key parts include the MAX17048. By type, the board carries 4 resistors, 3 capacitors, 2 ICs, 2 switches and 1 transistor.

It belongs with the iot & wireless, wearables and sensors designs in this gallery.

From the project

Este es el repositorio dedicado al proyecto del wearable para Capstone 2026-1 G10

SupaClock es un sistema de salud inteligente usable (wearable) de pulsera desarrollado como parte del curso IEE2463. Su propósito es capturar biometría crítica en tiempo real, procesarla tanto en el dispositivo mediante técnicas de Inteligencia Artificial en el borde (TinyML), enviarla vía Bluetooth Low Energy (BLE) a una aplicación móvil de compañía y respaldarla de forma segura en la nube.

Main components on the SupaClock Carrier v1 - PCB 67x85mm

XIAO-ESP32-S3MAX17048

SupaClock Carrier v1 - PCB 67x85mm bill of materials (BOM)

30 components, 21 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
XIAO-ESP32-S3
U1
1
MAX17048
U2
1
2N7002
Q1
1
10uF
C_DISP1
2
100nF
C_DISP2, C_RST1
1
1uF
C_FG1
1
10nF
C_FG2
1
CONN_BATT
J_BAT1
1
SensorBoard_Conn
J_CONN_SENSOR1
1
ST7789_24P
J_FPC1
1
GY-BMI160
J_IMU1
1
1k
R_FG1
1
100
R_FG2
6
10k
R_FG_ALT1, R_FG_QST1, R_GATE1, R_IM1, R_RD1, R_RST1
1
22
R_LEDA1
1
SELECT
SW1
1
NEXT
SW2
1
10UF
10uF
C2
2
100NF
100nF
C4, C5
2
4.7K
4.7k
R1, R2
Show 1 more
QtyPartRefs
2
10K
10k
R3, R4

SupaClock Carrier v1 - PCB 67x85mm design files

The KiCad project lives in the ArticunoFruna/SupaClock_IEE2463 repository on GitHub; these links point at the commit this page was built from.

SupaClock Carrier v1 - PCB 67x85mm: common questions

What microcontroller does the SupaClock Carrier v1 - PCB 67x85mm use?

The SupaClock Carrier v1 - PCB 67x85mm is built around the XIAO-ESP32-S3, from the ESP32 family.

How big is the SupaClock Carrier v1 - PCB 67x85mm?

The SupaClock Carrier v1 - PCB 67x85mm measures 40 × 48 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the SupaClock Carrier v1 - PCB 67x85mm?

30 components, from 21 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the SupaClock Carrier v1 - PCB 67x85mm design files?

From the ArticunoFruna/SupaClock_IEE2463 repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the SupaClock Carrier v1 - PCB 67x85mm design in my own project?

The repository has no license, so all rights stay with ArticunoFruna. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the SupaClock Carrier v1 - PCB 67x85mm without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug ESP32 firmware against it before you order a PCB.

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