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XIAO ESP32S3 V1.5

ArticunoFruna·SupaClock_IEE2463·docs/202003751_XIAO ESP32S3_v1.4_SCH&PCB_260226/202003753_XIAO ESP32S3 Sense_v1.5_SCH&PCB_260226/XIAO ESP32S3_V1.5.kicad_pcb

XIAO ESP32S3 V1.5 PCB layout, top view — open source ESP32 board by ArticunoFruna

About the XIAO ESP32S3 V1.5 PCB

XIAO ESP32S3 V1.5 is an open source ESP32 PCB design by ArticunoFruna, published on GitHub. It is a 4-layer board measuring 17.8 × 21.1 mm, with 70 components from 45 distinct parts.

Its main chip is the LP0404N3T5G, from the ESP32 family. Other key parts include the AD8232, SGM6029CYG/TR, SGM40567-4.2XG/TR, GD25Q64ENIGR and XIAO-Add-On. By type, the board carries 28 capacitors, 12 resistors, 8 test points, 5 ICs, 5 inductors and 2 relays.

It belongs with the iot & wireless, wearables and sensors designs in this gallery.

From the project

Este es el repositorio dedicado al proyecto del wearable para Capstone 2026-1 G10

SupaClock es un sistema de salud inteligente usable (wearable) de pulsera desarrollado como parte del curso IEE2463. Su propósito es capturar biometría crítica en tiempo real, procesarla tanto en el dispositivo mediante técnicas de Inteligencia Artificial en el borde (TinyML), enviarla vía Bluetooth Low Energy (BLE) a una aplicación móvil de compañía y respaldarla de forma segura en la nube.

Main components on the XIAO ESP32S3 V1.5

AD8232SGM6029CYG/TRSGM40567-4.2XG/TRGD25Q64ENIGRXIAO-Add-On

XIAO ESP32S3 V1.5 bill of materials (BOM)

70 components, 45 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
AD8232
ESP32-S3R8
U1
1
SGM6029CYG/TR
U3
1
SGM40567-4.2XG/TR
U4
1
GD25Q64ENIGR
U5
1
XIAO-Add-On
U9
1
LP0404N3T5G
Q1
1
40MHz/306011364
X1
1
DF40C-30DP-0.4V(51)
J3
1
U.FL-R-SMT-1
ANT1
1
VBAT
BAT0
1
GND
GND0
2
SKTAAAE010/311021459
K1, K2
8
TEST-POINT'4545'
TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8
1
UBF31-0171
USB0
1
RED
CHG0
1
LMBR4010BST5G
D2
1
Yellow
D3
1
2nH
L1
1
3.3nH
L2
1
DNP
L3
Show 25 more
QtyPartRefs
1
470nH
L4
1
24nH
L5
1
1.5NF
DNP
C1
1
1NF
DNP
C2
1
10NF
2.2uF
C3
2
0.33UF
4.7uF
C4, C6
1
0.1UF
4.7uF
C5
1
0.1UF
10pF
C7
2
10pF
C8, C28
3
2.2uF
C9, C13, C16
4
1uF
C10, C21, C25, C26
8
100nF
C11, C14, C15, C19, C22, C23, C29, C30
1
10nF
C12
2
DNP
C17, C20
1
1pF
C18
2
10M
5.1K
R1, R2
2
180K
22R
R3, R4
1
499R
R6
1
10K
R7
1
100K
10K
R8
1
100K
R9
1
10M
220K
R10
1
10M
10K
R11
1
10M
249K
R13
1
10K
1.5K
R15

XIAO ESP32S3 V1.5 design files

The KiCad project lives in the ArticunoFruna/SupaClock_IEE2463 repository on GitHub; these links point at the commit this page was built from.

XIAO ESP32S3 V1.5: common questions

What microcontroller does the XIAO ESP32S3 V1.5 use?

The XIAO ESP32S3 V1.5 is built around the LP0404N3T5G, from the ESP32 family.

How big is the XIAO ESP32S3 V1.5 PCB?

The XIAO ESP32S3 V1.5 measures 17.8 × 21.1 mm, has 4 copper layers and is 1.6 mm thick.

How many components are on the XIAO ESP32S3 V1.5?

70 components, from 45 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the XIAO ESP32S3 V1.5 design files?

From the ArticunoFruna/SupaClock_IEE2463 repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the XIAO ESP32S3 V1.5 design in my own project?

The repository has no license, so all rights stay with ArticunoFruna. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the XIAO ESP32S3 V1.5 without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug ESP32 firmware against it before you order a PCB.

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