2 open source boards using the XIAO-ESP32-S3
Real designs built with the XIAO-ESP32-S3, from public GitHub projects: a quick way to see how others power, decouple and connect it. Each board comes with its KiCad files, full parts list and a render — and you can simulate its firmware on HardLabs.
ESP32SupaClock Carrier v1 - PCB 67x85mm
ArticunoFruna
40 × 48 mm30 parts2LNo license0
ESP32SupaClock Carrier v1 - PCB 67x85mm
85 × 67 mm20 parts2LNo license0
The XIAO-ESP32-S3 in open source designs
The gallery holds 2 open source boards using the XIAO-ESP32-S3 from 1 GitHub repository; a typical one measures about 62.5 × 57.5 mm and carries around 25 components.
100% are two-layer designs, the rest use four layers or more, and 0% carry an open source license.
The most starred is SupaClock Carrier v1 - PCB 67x85mm by ArticunoFruna.
Microcontrollers on boards using the XIAO-ESP32-S3
What boards using the XIAO-ESP32-S3 are built for
XIAO-ESP32-S3: common questions
Where can I find a XIAO-ESP32-S3 reference design?
Each of the 2 boards on this page is a real design using the XIAO-ESP32-S3. Open one to see how it is wired up, with the full BOM, a render of the layout and links to its KiCad files.
Which microcontrollers do boards using the XIAO-ESP32-S3 use?
Most are built on ESP32 (2).
How big is a typical board using the XIAO-ESP32-S3?
The median is 62.5 × 57.5 mm, and 100% are two-layer designs.
What is the most popular open source board using the XIAO-ESP32-S3?
By GitHub stars, SupaClock Carrier v1 - PCB 67x85mm by ArticunoFruna, with 0 stars.
Can I simulate one of these boards using the XIAO-ESP32-S3 before building it?
Yes. HardLabs turns a board's netlist and BOM into a working simulation, so you can boot and test firmware against it with no hardware on your desk.