PULP

About the PULP PCB

PULP is an open source RP2040/RP2350 PCB design by JAS-UCF, published on GitHub under the CERN-OHL-S-2.0 license. It is a 2-layer board measuring 84 × 38.1 mm, with 68 components from 28 distinct parts.

Its main chip is the RP2040, from the RP2040/RP2350 family. Other key parts include the HMC5883L, MAX-M8Q, AP7361C-33E and W25Q128JVS. By type, the board carries 23 resistors, 22 capacitors, 7 connectors, 5 ICs, 4 diodes and 3 transistors.

From the project

kicad project that contains a PCB layout, in hopes of over-optimizing the GNOR race

KiCAD project that contains a PCB layout, in hopes of over-optimizing the GNOR race

- RP2040 processor DONE - compass module DONE - GPS module DONE - PINOUT for I2C Bus 0 & 1 DONE - PINOUT for PWM out MotorLeft & MotorRight (2x3 Pins) DONE - PINOUT for 3S Battery Power (External) ; Need to add regulator to help power the board DONE - PINOUT for 6 GPIO pins DONE - USB-C for programming and power DONE

Main components on the PULP

HMC5883L RP2040 MAX-M8Q AP7361C-33E W25Q128JVS

PULP bill of materials (BOM)

68 components, 28 distinct parts.

Qty	Part	Footprint	Refs
1	HMC5883L	HMC5883L	U1
1	RP2040	QFN-56-1EP_7x7mm_P0.4mm_EP3.2x3.2mm	U2
1	MAX-M8Q	ublox_MAX	U3
1	AP7361C-33E	SOT-223-3_TabPin2	U4
1	W25Q128JVS	SOIC-8_5.23x5.23mm_P1.27mm	U5
3	BSS138	SOT-23	Q1, Q2, Q3
1	ASE-12.0MHz	Oscillator_SMD_Abracon_ASE-4Pin_3.2x2.5mm	X2
1	Conn_Coaxial	U.FL_Molex_MCRF_73412-0110_Vertical	J1
2	Conn_01x02_Pin	PinHeader_1x02_P2.54mm_Horizontal	J2, J3
2	Conn_01x03_Pin	PinHeader_1x03_P2.54mm_Horizontal	J4, J5
1	Conn_01x09_Pin	PinHeader_1x09_P2.54mm_Vertical	J6
1	USB_C_Receptacle	USB_C_Receptacle_CNCTech_C-ARA1-AK51X	J7
2	SW_Push	SW_Push_SPST_NO_Alps_SKRK	SW1, SW2
2	ESD9B5.0ST5G	D_SOD-923	D1, D2
1	LED_ARGB	LED_RGB_1210	D3
1	1A	D_1812_4532Metric	D4
1	27nH	L_0201_0603Metric	L1
2	0.1uF	C_0201_0603Metric	C1, C3
3	4.7uF	C_0201_0603Metric	C2, C5, C7
1	10nF	C_0201_0603Metric	C4

Show 8 more

Qty	Part	Footprint	Refs
16	1uF	C_0201_0603Metric	C6, C8, C15, C16, C17, C18, C19, C20 +8
2	4.7K	R_0201_0603Metric	R1, R2
1	10	R_0201_0603Metric	R3
2	5.1K	R_0201_0603Metric	R4, R5
3	10K	R_0201_0603Metric	R6, R10, R11
2	1K	R_0201_0603Metric	R7, R8
3	510	R_0201_0603Metric	R9, R19, R20
10	27	R_0201_0603Metric	R12, R13, R14, R15, R16, R17, R18, R21 +2

PULP design files

The KiCad project lives in the JAS-UCF/PULP repository on GitHub; these links point at the commit this page was built from.

Layoutpulp.kicad_pcb
Schematicpulp.kicad_sch

PULP: common questions

What microcontroller does the PULP use?

The PULP is built around the RP2040, from the RP2040/RP2350 family.

How big is the PULP PCB?

The PULP measures 84 × 38.1 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the PULP?

68 components, from 28 distinct parts. The full bill of materials is listed on this page.

Where can I download the PULP design files?

From the JAS-UCF/PULP repository on GitHub, which has the KiCad layout and the schematic; the links under Design files point to each one.

Can I use the PULP design in my own project?

Yes, under the terms of its CERN-OHL-S-2.0 license, which JAS-UCF chose for the repository.

Can I test firmware for the PULP without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug RP2040/RP2350 firmware against it before you order a PCB.