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RSA-Intern-HW-Acelerografo ESP32

RedSismicaAustro·RSA-Intern-HW-Acelerografo_ESP32_KiCad·KiCad/projects/Acelerografo_ESP32/Acelerografo_ESP32.kicad_pcb

RSA-Intern-HW-Acelerografo ESP32 PCB layout, top view — open source ESP32 board by RedSismicaAustro

About the RSA-Intern-HW-Acelerografo ESP32 PCB

RSA-Intern-HW-Acelerografo ESP32 is an open source ESP32 PCB design by RedSismicaAustro, published on GitHub. It is a 2-layer board measuring 101.5 × 90 mm, with 63 components from 34 distinct parts.

Its main chip is the ESP32-WROOM-32, from the ESP32 family. Other key parts include the DS3231M, ADXL355Z, LD1117S33TR_SOT223, MP2307 and CH340G. By type, the board carries 19 capacitors, 18 resistors, 7 ICs, 7 diodes, 5 connectors and 2 switches.

From the project

Este repositorio contiene el espacio de trabajo, documentación de referencia y material de apoyo para el desarrollo de la pasantía de Joel Suárez en la Red Sísmica del Austro (RSA).

Este repositorio contiene el espacio de trabajo, documentación de referencia y material de apoyo para el desarrollo de la pasantía de Joel Suárez en la Red Sísmica del Austro (RSA).

El objetivo central es capturar, auditar, optimizar y estandarizar el diseño del Sistema Acelerográfico con ESP32 (SMD) en el entorno KiCad 10, garantizando que el diseño sea 100% compatible con el firmware de adquisición original y esté preparado para ensamblaje automático (PCBA) en JLCPCB.

Main components on the RSA-Intern-HW-Acelerografo ESP32

ESP32-WROOM-32DS3231MADXL355ZLD1117S33TR_SOT223MP2307CH340G74LVC125

RSA-Intern-HW-Acelerografo ESP32 bill of materials (BOM)

63 components, 34 distinct parts.

QtyPartRefs
1
ESP32-WROOM-32
U1
1
DS3231M
U2
1
ADXL355Z
U3
1
LD1117S33TR_SOT223
U4
1
MP2307
U5
1
CH340G
U6
1
74LVC125
U7
1
Conn_01x02
J1
1
Conn_01x04_Pin
J6
1
USB_C_Receptacle
J7
2
Conn_01x05_Pin
J17, J18
1
Battery
BT1
1
GPS_BREAKOUT_V3
GPS1
1
~
MicroSD1
1
200k
RVe1
2
SW_Push
SW1, SW2
5
ES1D
D1, D2, D5, D6, D7
2
LED
D3, D4
1
2uH
L1
8
100nF
C1, C4, C12, C13, C14, C15, C17, C19
Show 14 more
QtyPartRefs
3
10uF
C2, C8, C16
2
12uF
C3, C7
1
4.7nF
C5
1
10nF
C6
1
200nF
C9
2
100uF
C10, C11
1
1uF
C18
2
8.2k
R1, R3
1
100k
R2
6
4.7k
R4, R6, R14, R15, R16, R17
2
10k
R5, R9
2
5.1k
R7, R8
4
3.3k
R10, R11, R12, R13
1
200
R18

RSA-Intern-HW-Acelerografo ESP32 design files

The KiCad project lives in the RedSismicaAustro/RSA-Intern-HW-Acelerografo_ESP32_KiCad repository on GitHub; these links point at the commit this page was built from.

RSA-Intern-HW-Acelerografo ESP32: common questions

What microcontroller does the RSA-Intern-HW-Acelerografo ESP32 use?

The RSA-Intern-HW-Acelerografo ESP32 is built around the ESP32-WROOM-32, from the ESP32 family.

How big is the RSA-Intern-HW-Acelerografo ESP32 PCB?

The RSA-Intern-HW-Acelerografo ESP32 measures 101.5 × 90 mm, has 2 copper layers and is 1.6 mm thick.

How many components are on the RSA-Intern-HW-Acelerografo ESP32?

63 components, from 34 distinct parts. The full bill of materials is listed on this page.

Where can I download the RSA-Intern-HW-Acelerografo ESP32 design files?

From the RedSismicaAustro/RSA-Intern-HW-Acelerografo_ESP32_KiCad repository on GitHub, which has the KiCad layout and the schematic; the links under Design files point to each one.

Can I use the RSA-Intern-HW-Acelerografo ESP32 design in my own project?

The repository has no license, so all rights stay with RedSismicaAustro. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the RSA-Intern-HW-Acelerografo ESP32 without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug ESP32 firmware against it before you order a PCB.

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