Placement review plot
beleata·fpga-led-panel-sram·hardware/pico-panel/preview/placement-review-plot.kicad_pcb
About the Placement review plot PCB
Placement review plot is an open source RP2040/RP2350 PCB design by beleata, published on GitHub. It is a 2-layer board measuring 57.8 × 46.1 mm, with 77 components from 32 distinct parts.
Its main chip is the RP2040, from the RP2040/RP2350 family. Other key parts include the W25Q64JVSSIQ, USBLC6-2SC6, AP63203WU-7 and SN65HVD75DR. By type, the board carries 39 resistors, 20 capacitors, 5 ICs, 5 connectors, 3 diodes and 2 switches.
From the project
iCE40HX1K 64x32 ICND1065L RGB panel with double-buffered SRAM and 2 Mbaud UART image upload
Development snapshot, 2026-09-25. NOT FOR MANUFACTURE.
A custom two-layer 88 x 46.1 mm controller for the tested 64 x 32 ICND1065L LED panel. Bare RP2040, 8 MiB flash, vertical USB-C, non-isolated RS-485, W5500 Ethernet and a vertical HanRun HR963380AE integrated-magnetics jack. KiCad 10.0.6 project, 103 components. The custom PCB has not been fabricated or tested; the working YD-RP2040 module firmware is a separate result.

Main components on the Placement review plot
Placement review plot bill of materials (BOM)
77 components, 32 distinct parts — part numbers from the project's BOM.
| Qty | Part | Footprint | Refs |
|---|---|---|---|
| 1 | RP2040 | QFN-56-1EP_7x7mm_P0.4mm_EP3.2x3.2mm | U1 |
| 1 | W25Q64JVSSIQ | SOIC-8_5.3x5.3mm_P1.27mm | U2 |
| 1 | USBLC6-2SC6 | SOT-23-6 | U3 |
| 1 | AP63203WU-7 AP2112K-3.3 | SOT-23-5 | U4 |
| 1 | SN65HVD75DR | SOIC-8_3.9x4.9mm_P1.27mm | U7 |
| 1 | C20625731 ABM8-272-T3 12MHz | Crystal_SMD_3225-4Pin_3.2x2.5mm | Y1 |
| 1 | PANEL BOTTOM 2x8 | PinSocket_2x08_P2.54mm_Vertical | J1 |
| 1 | C3151748 USB-C VERTICAL H6.5 | USB_C_SHOUHAN_TYPE-C_16PLT-H6.5_Vertical | J2 |
| 1 | PANEL POWER +5V GND | PinHeader_1x02_P2.54mm_Vertical | J3 |
| 1 | SWD 3V3 GND CLK IO RUN | PinHeader_1x05_P2.54mm_Vertical | J4 |
| 1 | RS485 A B GND | PinHeader_1x03_P2.54mm_Vertical | J5 |
| 1 | C70076 PTC 0.5A | Fuse_1206_3216Metric | F1 |
| 1 | TERM 120R | PinHeader_1x02_P2.54mm_Vertical | JP1 |
| 1 | BOOTSEL | SW_SPST_TL3342 | SW1 |
| 1 | RESET | SW_SPST_TL3342 | SW2 |
| 1 | C2297 STATUS green | LED_0805_2012Metric | D1 |
| 1 | SS14 | D_SMA | D2 |
| 1 | SM712 | SOT-23 | D4 |
| 2 | 15P 15p | C_0603_1608Metric | C1, C2 |
| 2 | 100N 100n | C_0603_1608Metric | C3, C22 |
Show 12 more
| Qty | Part | Footprint | Refs |
|---|---|---|---|
| 11 | 100N 100n | C_0402_1005Metric | C4, C5, C6, C7, C8, C9, C10, C11 +3 |
| 3 | 1u | C_0603_1608Metric | C15, C16, C17 |
| 1 | C1713 4.7u | C_0603_1608Metric | C18 |
| 1 | C29277 4.7u | C_0603_1608Metric | C19 |
| 3 | 10K 10k | R_0603_1608Metric | R1, R3, R18 |
| 3 | 1k | R_0603_1608Metric | R2, R4, R5 |
| 2 | 5.1K 5.1k | R_0603_1608Metric | R6, R7 |
| 2 | 27 | R_0603_1608Metric | R8, R9 |
| 4 | 100K 100k | R_0603_1608Metric | R10, R11, R12, R13 |
| 1 | C17909 120 0.25W | R_1206_3216Metric | R19 |
| 12 | 33 | R_0603_1608Metric | R20, R21, R22, R23, R24, R25, R26, R27 +4 |
| 12 | 47K 47k | R_0603_1608Metric | R40, R41, R42, R43, R44, R45, R46, R47 +4 |
Placement review plot design files
The KiCad project lives in the beleata/fpga-led-panel-sram repository on GitHub; these links point at the commit this page was built from.
Placement review plot: common questions
What microcontroller does the Placement review plot use?
The Placement review plot is built around the RP2040, from the RP2040/RP2350 family.
How big is the Placement review plot PCB?
The Placement review plot measures 57.8 × 46.1 mm, has 2 copper layers and is 0.8 mm thick.
How many components are on the Placement review plot?
77 components, from 32 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.
Where can I download the Placement review plot design files?
From the beleata/fpga-led-panel-sram repository on GitHub, which has the KiCad layout and the BOM; the links under Design files point to each one.
Can I use the Placement review plot design in my own project?
The repository has no license, so all rights stay with beleata. Use it as a reference, and ask the author before reusing the design.
Can I test firmware for the Placement review plot without the hardware?
Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug RP2040/RP2350 firmware against it before you order a PCB.
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