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Ethernet fit plot

beleata·fpga-led-panel-sram·hardware/pico-panel/preview/ethernet-fit-plot.kicad_pcb

Ethernet fit plot PCB layout, top view — open source RP2040/RP2350 board by beleata
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About the Ethernet fit plot PCB

Ethernet fit plot is an open source RP2040/RP2350 PCB design by beleata, published on GitHub. It is a 2-layer board measuring 57.8 × 46.1 mm, with 79 components from 34 distinct parts.

Its main chip is the RP2040, from the RP2040/RP2350 family. Other key parts include the W25Q64JVSSIQ, USBLC6-2SC6, AP63203WU-7, SN65HVD75DR and W5500. By type, the board carries 39 resistors, 20 capacitors, 6 ICs, 6 connectors, 3 diodes and 2 switches.

From the project

iCE40HX1K 64x32 ICND1065L RGB panel with double-buffered SRAM and 2 Mbaud UART image upload

Development snapshot, 2026-09-25. NOT FOR MANUFACTURE.

A custom two-layer 88 x 46.1 mm controller for the tested 64 x 32 ICND1065L LED panel. Bare RP2040, 8 MiB flash, vertical USB-C, non-isolated RS-485, W5500 Ethernet and a vertical HanRun HR963380AE integrated-magnetics jack. KiCad 10.0.6 project, 103 components. The custom PCB has not been fabricated or tested; the working YD-RP2040 module firmware is a separate result.

Ethernet fit plot, from the project README
From the project README

Main components on the Ethernet fit plot

RP2040W25Q64JVSSIQUSBLC6-2SC6AP63203WU-7SN65HVD75DRW5500

Ethernet fit plot bill of materials (BOM)

79 components, 34 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
RP2040
U1
1
W25Q64JVSSIQ
U2
1
USBLC6-2SC6
U3
1
AP63203WU-7
AP2112K-3.3
U4
1
SN65HVD75DR
U7
1
W5500
W5500 - FIT STUDY ONLY
U8
1
C20625731
ABM8-272-T3 12MHz
Y1
1
PANEL BOTTOM 2x8
J1
1
C3151748
USB-C VERTICAL H6.5
J2
1
PANEL POWER +5V GND
J3
1
SWD 3V3 GND CLK IO RUN
J4
1
RS485 A B GND
J5
1
C19724763
HR963380AE - CIRCUIT PENDING
J6
1
C70076
PTC 0.5A
F1
1
TERM 120R
JP1
1
BOOTSEL
SW1
1
RESET
SW2
1
C2297
STATUS green
D1
1
SS14
D2
1
SM712
D4
Show 14 more
QtyPartRefs
2
15P
15p
C1, C2
2
100N
100n
C3, C22
11
100N
100n
C4, C5, C6, C7, C8, C9, C10, C11 +3
3
1u
C15, C16, C17
1
C1713
4.7u
C18
1
C29277
4.7u
C19
3
10K
10k
R1, R3, R18
3
1k
R2, R4, R5
2
5.1K
5.1k
R6, R7
2
27
R8, R9
4
100K
100k
R10, R11, R12, R13
1
C17909
120 0.25W
R19
12
33
R20, R21, R22, R23, R24, R25, R26, R27 +4
12
47K
47k
R40, R41, R42, R43, R44, R45, R46, R47 +4

Ethernet fit plot design files

The KiCad project lives in the beleata/fpga-led-panel-sram repository on GitHub; these links point at the commit this page was built from.

Ethernet fit plot: common questions

What microcontroller does the Ethernet fit plot use?

The Ethernet fit plot is built around the RP2040, from the RP2040/RP2350 family.

How big is the Ethernet fit plot PCB?

The Ethernet fit plot measures 57.8 × 46.1 mm, has 2 copper layers and is 0.8 mm thick.

How many components are on the Ethernet fit plot?

79 components, from 34 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the Ethernet fit plot design files?

From the beleata/fpga-led-panel-sram repository on GitHub, which has the KiCad layout and the BOM; the links under Design files point to each one.

Can I use the Ethernet fit plot design in my own project?

The repository has no license, so all rights stay with beleata. Use it as a reference, and ask the author before reusing the design.

Can I test firmware for the Ethernet fit plot without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug RP2040/RP2350 firmware against it before you order a PCB.

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