IO-SDR

rishivg·IO-SDR·KICAD Design Files/IO_SDR_1.1.kicad_pcb

IO-SDR PCB layout, top view — open source FPGA board by rishivg
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About the IO-SDR PCB

IO-SDR is an open source FPGA PCB design by rishivg, published on GitHub under the CERN-OHL-S-2.0 license. It is a 8-layer board measuring 99.4 × 60 mm, with 309 components from 99 distinct parts.

Its main chip is the XC7Z010-1CLG400I, from the FPGA family. Other key parts include the TCMT1107, SY6280AAC, TCS4615, TPS7A8101DRBT and RT9193-33B. By type, the board carries 146 capacitors, 52 resistors, 20 ICs, 14 inductors, 13 connectors and 4 transistors.

It belongs with the rf & radio designs in this gallery.

From the project

Open-Source software-defined FPGA radio hardware platform

IO-SDR is an open-source software-defined FPGA radio hardware platform that serves as a successor to the Pluto SDR Learning Module. Support includes and is not limited to:

- dual multichannel transmission and reception - Gigabit Ethernet connection - Embedded Linux SoC development - GNU Radio blocks

IO-SDR, from the project README
From the project README

Main components on the IO-SDR

IO-SDR bill of materials (BOM)

309 components, 99 distinct parts — part numbers from the project's BOM.

QtyPartRefs
1
TCMT1107
U1
1
SY6280AAC
U2
4
TCS4615
U3, U4, U7, U8
2
TPS7A8101DRBT
U5, U6
3
RT9193-33B
U9, U11, U17
1
RTL8211E-VB-CG
U10
1
AD9361BBCZ
U12
1
USB3320C-EZK
USB3320C-EZK-TR
U13
1
XC7Z010-1CLG400I
U14
1
MX25U1635EZNI-10G
U15
1
TXS02612RTWR
U16
1
H5TQ4G63AFR
U18
1
MS5611-01BA
U19
1
BNO085
U21
2
S8050
Q1, Q2
2
~
Q3, Q4
1
TSX-3225_25.0000MF10P-C0
25MHz
Y1
1
25MHZ
25MHz
Y2
1
32.768KHZ
32.768kHz
Y3
2
10118193-0001LF
J1, J2
Show 79 more
QtyPartRefs
1
CONN_01X03_SHIELDED
Conn_01x03_Shielded
J3
3
CON12-254
J4, J5, J6
1
HR911130A1
J7
1
73412-0110
J8
4
RF2-49B-T-00-50-G-HDW
J9, J10, J11, J12
1
502570-0893
J13
3
0.1UF
0.1uF
CA1, CA8, CA11
3
10UF
10uF
CA2, CA7, CA9
2
12PF
12pF
CA3, CA4
2
18PF
18pF
CA5, CA6
1
4.7UF
4.7uF
CA10
1
ASDMB-33.333MHZ-LC-T
CY1
1
33.333MHZ
33.333MHz
CY2
3
HR8031GS6
QA1, QA2, QA3
2
2.4K
RA1, RA2
1
4.7K
RA3
1
5.1K
RA4
1
0R
RA5
1
10K
RA6
1
1M
RA7
1
14.3K
RA8
11
20K
RA9, RA11, RA13, RA15, RA16, RA17, RA21, RA22 +3
1
8.06K
RA10
3
1K
RA12, RA14, RA18
2
33R
RA19, RA20
2
100K
RA24, RA26
2
4.7K
RA28, RA29
1
SW_DIP_X02
SW_DIP_x02
SW1
4
TCM1-63AX_
T1, T2, T3, T4
3
HR02X5V
V1, V2, V3
1
SUPK24
D1
1
SUP5522F
D2
2
LED6
D3, D4
5
2.2UH
2.2uH
L1, L4, L7, L8, L9
1
R0603
L2
2
R0805
L3, L5
1
R0402
L6
1
BLM18PG181SN1
L10
2
330NH
330nH
L11, L13
2
330NF
330nF
L12, L14
2
22UF
22uF
C1, C2
1
100UF
100uF
C3
1
22UF
22uF
C4
4
10UF
10uF
C5, C51, C108, C109
16
10UF
10uF
C6, C11, C12, C13, C15, C16, C18, C19 +8
2
10UF
10uF
C7, C8
1
1UF
1uF
C9
6
100PF
100pF
C10, C14, C30, C31, C119, C120
23
0.1UF
0.1uF
C17, C20, C38, C40, C41, C42, C43, C44 +15
4
47UF
47uF
C21, C23, C26, C27
30
10NF
10nF
C22, C24, C52, C54, C55, C60, C61, C64 +22
1
10UF
10uF
C36
2
4.7UF
4.7uF
C37, C50
17
100NF
100nF
C39, C80, C81, C90, C91, C99, C100, C105 +9
1
0.1UF
0.1uF
C53
12
1UF
1uF
C56, C57, C58, C62, C63, C68, C70, C111 +4
12
18PF
18pF
C65, C67, C72, C73, C82, C83, C84, C85 +4
4
1NF
1nF
C76, C77, C78, C79
5
10UF
10uF
C94, C95, C96, C113, C135
2
22PF
22pf
C149, C150
1
33R
R1
6
10K
R2, R3, R7, R15, R22, R56
3
7.5K
R4, R8, R10
1
2K
R5
1
20K
R6
2
12K
R9, R11
1
3.3K
R12
10
4.7K
R13, R39, R40, R41, R42, R43, R46, R51 +2
1
15K
R14
8
4K7
R16, R17, R18, R19, R20, R24, R25, R26
1
1K5
R21
1
2.49K%1
R23
2
510R R0402 5%
R27, R28
1
50K
R29
1
ESD
R30
2
1R
R31, R32
6
2.4K
R33, R34, R35, R36, R44, R45
3
80.5R
R37, R38, R48
1
240R
R47

IO-SDR design files

The KiCad project lives in the rishivg/IO-SDR repository on GitHub; these links point at the commit this page was built from.

IO-SDR: common questions

What microcontroller does the IO-SDR use?

The IO-SDR is built around the XC7Z010-1CLG400I, from the FPGA family.

How big is the IO-SDR PCB?

The IO-SDR measures 99.4 × 60 mm, has 8 copper layers and is 1.620266 mm thick.

How many components are on the IO-SDR?

309 components, from 99 distinct parts, with part numbers taken from the project's own BOM. The full bill of materials is listed on this page.

Where can I download the IO-SDR design files?

From the rishivg/IO-SDR repository on GitHub, which has the KiCad layout, the schematic and the BOM; the links under Design files point to each one.

Can I use the IO-SDR design in my own project?

Yes, under the terms of its CERN-OHL-S-2.0 license, which rishivg chose for the repository.

Can I test firmware for the IO-SDR without the hardware?

Yes. HardLabs builds a simulation of the board from its netlist and BOM, so you can run and debug FPGA firmware against it before you order a PCB.

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