1 open source board using the Logic-Level-Translator
Real designs built with the Logic-Level-Translator, from public GitHub projects: a quick way to see how others power, decouple and connect it. Each board comes with its KiCad files, full parts list and a render — and you can simulate its firmware on HardLabs.
zen451019The Logic-Level-Translator in open source designs
The gallery holds 1 open source boards using the Logic-Level-Translator from 1 GitHub repository; a typical one measures about 90 × 85 mm and carries around 17 components.
100% are two-layer designs, the rest use four layers or more, and 0% carry an open source license.
The most starred is SLAVE V-C NO INSOLATED by zen451019.
Microcontrollers on boards using the Logic-Level-Translator
What boards using the Logic-Level-Translator are built for
Logic-Level-Translator: common questions
Where can I find a Logic-Level-Translator reference design?
Each of the 1 boards on this page is a real design using the Logic-Level-Translator. Open one to see how it is wired up, with the full BOM, a render of the layout and links to its KiCad files.
Which microcontrollers do boards using the Logic-Level-Translator use?
Most are built on ESP32 (1).
How big is a typical board using the Logic-Level-Translator?
The median is 90 × 85 mm, and 100% are two-layer designs.
What is the most popular open source board using the Logic-Level-Translator?
By GitHub stars, SLAVE V-C NO INSOLATED by zen451019, with 1 stars.
Can I simulate one of these boards using the Logic-Level-Translator before building it?
Yes. HardLabs turns a board's netlist and BOM into a working simulation, so you can boot and test firmware against it with no hardware on your desk.