2 open source boards using the XIAO-ESP32-S3-DIP_UI
Real designs built with the XIAO-ESP32-S3-DIP_UI, from public GitHub projects: a quick way to see how others power, decouple and connect it. Each board comes with its KiCad files, full parts list and a render — and you can simulate its firmware on HardLabs.
ESP32Main 2026 V1
Gamu2124
156.7 × 149.9 mm127 parts2LNo license0
ESP32Main 2026 V1
156.7 × 149.9 mm127 parts2LNo license1
The XIAO-ESP32-S3-DIP_UI in open source designs
The gallery holds 2 open source boards using the XIAO-ESP32-S3-DIP_UI from 2 GitHub repositories; a typical one measures about 156.7 × 149.9 mm and carries around 127 components.
100% are two-layer designs, the rest use four layers or more, and 0% carry an open source license.
The most starred is Main 2026 V1 by Gamu2124.
Parts used alongside the XIAO-ESP32-S3-DIP_UI
Microcontrollers on boards using the XIAO-ESP32-S3-DIP_UI
What boards using the XIAO-ESP32-S3-DIP_UI are built for
XIAO-ESP32-S3-DIP_UI: common questions
Where can I find a XIAO-ESP32-S3-DIP_UI reference design?
Each of the 2 boards on this page is a real design using the XIAO-ESP32-S3-DIP_UI. Open one to see how it is wired up, with the full BOM, a render of the layout and links to its KiCad files.
What parts are used alongside the XIAO-ESP32-S3-DIP_UI?
The BD50FD0W_CAM, BD50FD0W_CPU, LM1117MP-3.3, LM1117MP-3.3_MODULE and XIAO-ESP32-S3-DIP_USS appear in the most repositories here.
Which microcontrollers do boards using the XIAO-ESP32-S3-DIP_UI use?
Most are built on ESP32 (2).
How big is a typical board using the XIAO-ESP32-S3-DIP_UI?
The median is 156.7 × 149.9 mm, and 100% are two-layer designs.
What is the most popular open source board using the XIAO-ESP32-S3-DIP_UI?
By GitHub stars, Main 2026 V1 by Gamu2124, with 1 stars.
Can I simulate one of these boards using the XIAO-ESP32-S3-DIP_UI before building it?
Yes. HardLabs turns a board's netlist and BOM into a working simulation, so you can boot and test firmware against it with no hardware on your desk.